or when the prefix register contains all zeros. In both
of these cases, a real address and its corresponding
absolute address are identical. CPU Signaling and Response
The CPU-signaling-and-response facility provides
for communications among CPUs by means of the
SIGNAL PROCESSOR instruction. It provides for
transmitting and receiving the signal, decoding a set
of assigned order codes, performing the specified
operation, and responding to the signaling CPU. If a CPU has the CPU-signaling-and-response
facility installed, it can address the SIGNAL PRO­ CESSOR fnstruction to itself. All orders are executed
as defined. Orders Twelve orders are provided for communications
among CPUs in a multiprocessing system. The or­
ders are specified in bit positions 24-31 of the
second-operand address of SIGNAL PROCESSOR and are ericoded as follows:
Code Order 00 Invalid and Unassigned 01 Sense 02 External Call 03 Emergency Signal 04 Start 05 Stop 06 Restart 07 Initial Program Reset 08 Program Reset 09 Stop and Store Status OA Initial Microprogram Load 08 I nitial CPU Reset OC CPU Reset
OD-FF I nvalid and Unassigned
The orders are defined as follows:
Sense: The addressed CPU presents its status to the
issuing CPU (see "Status Bits" in this chapter for a
definition of the bits). No other action is caused at
the addressed CPU. The status, if not all zeros, is
stored in the general register designated by the Rl
field, and condition code 1 is set; if all status bits are
zero, condition code 0 is set.
External Call: An "external call" external­
interruption condition is generated at the addressed CPU. The interruption condition becomes pending
during the execution of the SIGNAL PROCESSOR instruction. The associated interruption occurs when
the CPU is interruptible for that condition and does
not necessarily occur during the execution of the
SIGNAL PROCESSOR instruction. The address of
the CPU sending the signal is provided with the in-
terruption code when the interruption occurs. Only one external-call condition can be kept pending in a CPU at a time.
Emergency Signal: An "emergency-signal" external­
interruption condition is generated at the addressed CPU. The interruption condition becomes pending
during the execution of the SIGNAL PROCESSOR instruction. The associated interruption occurs when
the CPU is interruptible for that condition and does
not necessarily occur during the execution of the
SIGNAL PROCESSOR instruction. The address of
the CPU sending the signal is provided with the in­
terruption code when the interruption occurs. At any
one time the receiving CPU can keep pending one
emergency-signal condition for each CPU of the
multiprocessing system, including the receiving CPU itself.
Start: The addressed CPU is placed in the operating stqte (see "Stopped and Operating States" in the
chapter "System Control"). The order is effective
only when the addressed CPU is in the stopped
state, and the effect is unpredictable when the stopped
state has been entered by reset. The CPU does
not necessarily enter the operating state during the
execution of the SIGNAL PROCESSOR instruction.
Stop: The addressed CPU performs the stop func­
tion (see "Stopped and Operating States" in the
chapter "System Control"). The CPU does not
necessarily enter the stopped state during the execu­
tion of the SlGNAL PROCESSOR instruction. No
action is caused at the addressed CPU if that CPU is
in the stopped state when the order code is accepted.
Restarl: The addressed CPU performs the restart
function (see "Restart" in the chapter "I . ") Th C . nterruptIons. e PU does not necessarily
perform the function during the execution of the
SIGNAL PROCESSOR instruction.
Initial Program Reset: The addressed CPU per­
forms initial program reset (see "Resets" in the
chapter "System Control"). The execution of the
reset does not affect other CPUs and does not affect
channels not configured to the CPU being reset. The
reset operation is not necessarily completed during
the execution of the SIGNAL PROCESSOR instruc­
tion.
Program Reset: The addressed CPU performs pro­
gram reset (see "Resets" in the chapter" System
Control"). The execution of the reset does not affect
other CPUs and does not affect channels not config-
Multiprocessing 97
ured to the CPU being reset. The reset operation is
not necessarily completed during the execution of
the SIGNAL PROCESSOR instruction.
Stop and Store Status: The addressed CPU per­
forms the stop function, followed by the store··status function (see "Stopped and Operating States" and "Store Status" in the chapter "System The CPU does not necessarily complete the opera­
tion, or even enter the stopped state, during the exe­
cution of the SIGNAL PROCESSOR instruction.
Initial Mricroprogram Load (lMPL): The addressed CPU performs initial program reset and then initi­
ates the initial-microprogram-Ioad function. The
latter funetion is the same as that which is performed
as part of manual initial microprogram loading. If the
initial-mic:roprogram-Ioad function is not provided
on the addressed CPU, the order code is treated as
unassigned and invalid. The operation is not neces­
sarily completed during the execution of the SIG­ NAL PROCESSOR instruction.
Initial CPU Reset: The addressed CPU performs
initial CPU reset (see "Resets" in the chapter "System Control"). The execution of the reset does
not affect other CPUs and does not cause any chan­
nels, including those configured to the addressed CPU, to be reset. The reset operation is not neces­
sarily completed during the execution of the SIG­ NAL PROCESSOR instruction. CPU RE'Set: The addressed CPU performs CPU reset (see "Resets" in the chapter "System Con­
trol"). The execution of the reset does not affect
other CPUs and does not cause any channels, in­
cluding those configured to the addressed CPU, to
be reset. The reset operation is not necessarily com­
pleted during the execution of the SIGNAL PRO­ CESSOR instruction. Determining Response
Conditions Precluding Interpretation of the Order Code
The following situations determine the initiation of
the order. The sequence in which the situations are
listed is the order of priority for indicating concur­
rently existing situations:
1. The access path to the addressed CPU is busy
because a concurrently issued SIGNAL PROCESSOR instruction is using the CPU­ signaling-and-response facility. The concur­
rently issued instruction mayor may not have
been issued by or to the addressed CPU and
98 System/370 Principles of Operation
mayor may not have been issued to this CPU. The order is rejected. Condition code 2 is set.
2. The addressed CPU is not operational, that is,
the addressed CPU is not installed, is not con­
figured to the issuing CPU, or is in certain
customer-engineer test modes, or does not
have its power on. The order is rejected. Con­
dition code 3 is set.
3. One of the following conditions exists at the
addressed CPU: a. A previously issued start, stop, restart, or
stop-and-store-status order has been accept­
ed by the addressed CPU, and execution of
the order has not yet been completed.
b. A manual start, stop, restart, or store-status
function has been initiated at the addressed CPU, and the operation has not yet been
completed.
c. A manual initial-pro gram-load function has
been initiated at the addressed CPU, and
the reset portion, but not the program load
portion, of the operation has been complet­
ed.
If the currently specified order is a sense,
external call, emergency signal, start, stop,
restart, or stop and store status, the order is
rejected, and condition code 2 is set. If the
currently specified order is an IMPL, one of
the reset orders, or an unassigned or not­
implemented order, the order code is inter­
preted as described in the section "Status Bits."
4. One of the following conditions exists at the
addressed CPU: a. A previously issued initial-program-reset,
program-reset, IMPL, initial-CPU-reset, or CPU-reset order has been accepted by the
addressed CPU, and execution of the order
has not yet been completed.
b. A manual reset or IMPL function has been
initiated at the addressed CPU, and the
function has not yet been completed. The
term "manual reset function" includes the
reset portion of IPL. If the currently specified order is a sense,
external call, emergency signal, start, stop,
restart, or stop and store status, the order is
rejected, and condition code 2 is set. If the
currently specified order is an IMPL, one of
the reset orders, or an unassigned or not­
implemented order, either the order is re­
jected and condition code 2 is set or the or-
Previous Page Next Page