or when the prefix register contains all zeros. In both
of these cases, a real address and its corresponding
absolute address are identical.CPU Signaling and Response
The CPU-signaling-and-response facility provides
for communications amongCPUs by means of the
SIGNALPROCESSOR instruction. It provides for
transmitting and receiving the signal, decoding a set
of assigned order codes, performing the specified
operation, and responding to the signalingCPU. If a CPU has the CPU-signaling-and-response
facility installed, it can address the SIGNALPRO CESSOR fnstruction to itself. All orders are executed
as defined.Orders Twelve orders are provided for communications
amongCPUs in a multiprocessing system. The or
ders are specified in bit positions 24-31 of the
second-operand address of SIGNALPROCESSOR and are ericoded as follows:
CodeOrder 00 Invalid and Unassigned 01 Sense 02 External Call 03 Emergency Signal 04 Start 05 Stop 06 Restart 07 Initial Program Reset 08 Program Reset 09 Stop and Store Status OA Initial Microprogram Load 08 I nitial CPU Reset OC CPU Reset
OD-FFI nvalid and Unassigned
The orders are defined as follows:
Sense: The addressedCPU presents its status to the
issuingCPU (see "Status Bits" in this chapter for a
definition of the bits). No other action is caused at
the addressedCPU. The status, if not all zeros, is
stored in the general register designated by the Rl
field, and condition code 1 is set; if all status bits are
zero, condition code0 is set.
External Call: An "externalcall" external
interruption condition is generated at the addressedCPU. The interruption condition becomes pending
during the execution of the SIGNALPROCESSOR instruction. The associated interruption occurs when
theCPU is interruptible for that condition and does
not necessarily occur during the execution of the
SIGNALPROCESSOR instruction. The address of
theCPU sending the signal is provided with the in-
terruption code when the interruption occurs.Only one external-call condition can be kept pending in a CPU at a time.
Emergency Signal: An "emergency-signal" external
interruption condition is generated at the addressedCPU. The interruption condition becomes pending
during the execution of the SIGNALPROCESSOR instruction. The associated interruption occurs when
theCPU is interruptible for that condition and does
not necessarily occur during the execution of the
SIGNALPROCESSOR instruction. The address of
theCPU sending the signal is provided with the in
terruption code when the interruption occurs. At any
one time the receivingCPU can keep pending one
emergency-signal condition for eachCPU of the
multiprocessing system, including the receivingCPU itself.
Start: The addressedCPU is placed in the operating stqte (see "Stopped and Operating States" in the
chapter"System Control"). The order is effective
only when the addressedCPU is in the stopped
state, and the effect is unpredictable when the stopped
state has been entered by reset. TheCPU does
not necessarily enter the operating state during the
execution of the SIGNALPROCESSOR instruction.
Stop: The addressedCPU performs the stop func
tion (see"Stopped and Operating States" in the
chapter"System Control"). The CPU does not
necessarily enter the stopped state during the execu
tion of the SlGNALPROCESSOR instruction. No
action is caused at the addressedCPU if that CPU is
in the stopped state when the order code is accepted.
Restarl: The addressedCPU performs the restart
function (see"Restart" in the chapter "I . ") Th C . nterruptIons. e PU does not necessarily
perform the function during the execution of the
SIGNALPROCESSOR instruction.
Initial ProgramReset: The addressed CPU per
forms initial program reset (see"Resets" in the
chapter"System Control"). The execution of the
reset does not affect otherCPUs and does not affect
channels not configured to theCPU being reset. The
reset operation is not necessarily completed during
the execution of the SIGNALPROCESSOR instruc
tion.
ProgramReset: The addressed CPU performs pro
gramreset (see "Resets" in the chapter" System
Control"). The execution of the reset does not affect
otherCPUs and does not affect channels not config-
Multiprocessing 97
of these cases, a real address and its corresponding
absolute address are identical.
The CPU-signaling-and-response facility provides
for communications among
SIGNAL
transmitting and receiving the signal, decoding a set
of assigned order codes, performing the specified
operation, and responding to the signaling
facility installed, it can address the SIGNAL
as defined.
among
ders are specified in bit positions 24-31 of the
second-operand address of SIGNAL
Code
OD-FF
The orders are defined as follows:
Sense: The addressed
issuing
definition of the bits). No other action is caused at
the addressed
stored in the general register designated by the Rl
field, and condition code 1 is set; if all status bits are
zero, condition code
External Call: An "external
interruption condition is generated at the addressed
during the execution of the SIGNAL
the
not necessarily occur during the execution of the
SIGNAL
the
terruption code when the interruption occurs.
Emergency Signal: An "emergency-signal" external
interruption condition is generated at the addressed
during the execution of the SIGNAL
the
not necessarily occur during the execution of the
SIGNAL
the
terruption code when the interruption occurs. At any
one time the receiving
emergency-signal condition for each
multiprocessing system, including the receiving
Start: The addressed
chapter
only when the addressed
state, and the effect is unpredictable when the stopped
state has been entered by reset. The
not necessarily enter the operating state during the
execution of the SIGNAL
Stop: The addressed
tion (see
chapter
necessarily enter the stopped state during the execu
tion of the SlGNAL
action is caused at the addressed
in the stopped state when the order code is accepted.
Restarl: The addressed
function (see
perform the function during the execution of the
SIGNAL
Initial Program
forms initial program reset (see
chapter
reset does not affect other
channels not configured to the
reset operation is not necessarily completed during
the execution of the SIGNAL
tion.
Program
gram
Control"). The execution of the reset does not affect
other
Multiprocessing 97