The current PSW is replaced by the contents of the
doubleword at the location designated by the _ second-operand address.
If the new PSW specifies the basic-control (BC)
mode, information in bit positions 16-33 of the new PSW is not retained as the PSW is loaded. When the PSW is subsequently stored, these bit positions con­
tain the new interruption code and the instruction­
length code.
A serialization function is performed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs. No subsequent I instructions or their operands are accessed by this CPU until the execution of this instruction is com­
pleted.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
The value which is to be loaded by the instruction
is not checked for validity before it is loaded. How­
ever, immediately after loading, a specification ex­
ception is recognized, and a program interruption
occurs, when the value specifies the BC mode and
the BC facility is not installed, or when the value
specifies the EC mode and the contents of bit posi­
tions 0, 2-·4, 16-17, and 24-39 are not all zeros. In
these cases, the operation is completed, and the re­
sulting instruction-length code is zero.
Bits 8-15 of the instruction are ignored.
Resulting Condition Code: The code is set as speci­
fied in the new PSW loaded.
Program Exceptiom: Privileged operation
Access (fetch, operand 2)
Specification
Load Real Address
The real address corresponding to the second·,
operand address is inserted in the general register
designated by the R 1 field. The remaining high-order
bits of the register are set to zeros.
The logical address specified by the X2, B21 and
D2 fields is translated by means ofthe dynamic­
address-translation facility, regardless of whether
106 System/370 Principles of Operation
translation is specified in the PSW, and regardless of
whether the PSW specifies the BC or EC mode. The
translation is performed using the current contents
of control registers 0 and 1, but without the use of
the translation-look aside buffer (TLB). The reSUl­ tant 24-bit real address is inserted in bit positions
8-31 of the general register designated by the Rl
field, and bits 0-7 of the register are set to zeros.
The translated address is not inspected for resolu-
. tion, protection, or validity.
Condition code 0 is set when translation can be
completed, that is, when the entry in each table lies
within the specified table length and its I bit is zero.
When the I bit in the segment-table entry is one,
condition code 1 is set, and the real address of the
segment-table entry is placed in the register desig­
nated by the R 1 field. When the I bit in the page­
table entry is one, condition code 2 is set, and the
real address of the page-tabie entry is placed in the
register designated by the Rl field. When either the
segment-table entry or the page-table entry is out­
side the table, condition code 3 is set, and the regis­
ter designated by the R 1 field contains the real ad­
dress of the entry that would have been referred to if
the length violation did not occur. In all these cases,
the 24-bit address is placed in bit positions 8-31 of
the register, and the leftmost eight bits of the regis­
ter are set to zeros.
An addressing exception is recognized when the
address of the segment-table entry or page-table
entry designates a location outside the available
main storage of the installed system. A translation­
specification exception is recognized when bits 8-12
of control register 0 contain an invalid code, or the
segment-table entry or page-table entry has a format
error. For all these cases, the operation is sup­
pressed.
Resulting Condition Code:
o Translation available
1 Segment-table entry invalid (I bit is one)
2 Page-table entry invalid (I bit is one)
3 Segment-or page-table length violation
Program Exceptions: Operation (if the translation feature is not in­
stalled)
Privileged operation
Access (addressing for table-entry access and
translation specification only, operand 2)

Purge TLB PTLB [S] 8200 o 16 31
All information in the translation-Iookaside buffer
(TLB) of this CPU is made invalid. No change is
made to the contents of addressable storage or regis­
ters.
The TLB appears cleared of its original contents
for all following instructions. When the CPU does
not have a TLB, the instruction is equivalent to a
no-operation. The invalidation is not signaled to any
other CPU. A serialization function is performed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs. No subsequent
instructions, their operands, or dynamic-address­
translation entries are fetched by this CPU until the
execution of this instruction is complete.
Bits 16-31 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the translation feature is not in­
stalled)
Privileged operation
Read Direct
RDD [SI] 85
o 8 16 20 31
The contents of the 12 field are made available as
signal-out timing signals. A direct-in data byte is
accepted from an external device in the absence of a
hold signal and is placed in the location designated
by the operand address.
The contents of the 12 field are made available on
a set of eight signal-out lines as 0.5-microsecond to
1.0-microsecond timing signals. These signal-out
lines are also used in WRITE DIRECT. On a ninth
line (read out) a 0.5-microsecond to 1.0- microsecond timing signal is made available coinci­
dent with these timing signals. The read-out line is
distinct from the write-out line in WRITE DIRECT.
No checking bits are made available with the eight
instruction bits.
Eight data bits are accepted from a set of eight
direct-in lines when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least 0.5 microsecond. No checking bits
are accepted with data signals, but a checking-block
code is generated as the data is placed in storage.
When the hold signal is not removed, the CPU does
not complete the instruction.
A serialization function is performed before the
signals are made available and again after the first­
operand byte is placed in storage. CPU operation is
delayed until all previous accesses by this CPU to
main storage have been completed, as observed by
channels and other CPUs, and then the signal-out
timing signals are presented. No subsequent instruc­
tions or their operands are accessed by this CPU until the first operand byte has been placed in main
storage, as observed by channels and other CPUs. An excessively long instruction execution may
result in incomplete updating of the interval timer.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the direct-control feature is not
installed)
Privileged operation
Access (store, operand 1)
Reset Reference Bit
RRB [S] 8213
o 16 20 31
The reference bit is set to zero in the key in storage
associated with the block that is designated by the
second-operand address.
Bits 8-20 of the second-operand address desig­
nate a block of 2,048 bytes in real main storage. Bits 0-7 and 21-31 of the address are ignored.
The address designating the storage block, being a
real address, is not subject to dynamic address trans­
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The value of the remaining bits of the key, includ­
ing the change bit, is not affected.
System-Control Instructions 107