157-159. Address computation follows the rules of
address arithmetic. The address is not inspected for
access exceptions. Zeros are stored at location 156.
When the monitor-mask bit corresponding to the
class specified by bits 12-15 of the instruction is
zero, no interruption occurs, and the instruction is
executed as a no-operation.
Bit positions 8-11 of the instruction must contain
zeros; otherwise, a specification exception is recog­
nized, and the operation is suppressed.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Monitoring
Programming Notes
The monitoring function is useful in performing vari­
ous measurement functions; specifically, by implant­
ing MONITOR CALL instructions within the code,
tracing information can be generated indicating
which programs were executed, counting informa­
tion can be generated indicating how often particular
programs are used, and timing information can be
generated indicating how long a particular program
required for execution.
The monitor code provides a means of associating
descriptive information, in addition to the class num­
ber, with each MONITOR CALL instruction. With­
out the use of a base register, up to 4,096 distinct
monitor codes can be associated with a monitoring
interruption. With the base register designated by a
nonzero value in the Bt field, each monitoring inter­
ruption can be identified by a 24-bit code.
The monitor masks provide a means of disallow­
ing all interruptions due to MONITOR CALL or
allowing monitoring for all or selected classes.
Move
MVI Dt(Bt),Iz lSI] 92 I 12 B, 0, 0 8 16 20 31
MVC Dt(L,Bt),D2(B2) [SS] 02 L B, I 8
2 I 0 8 16 20 32 36 47
The second operand is placed in the first-operand
location.
Page of GA22-70004 Revised September 1, 1975
By TNL: GN22-0498
For MVC, each operand field is processed left to
right. When the operands overlap, the result is ob­
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of MVC; store, operand
1, MVI and MVC)
Programming Note
It is possible to propagate one character through an
entire field by having the first-operand field start
one character to the right of the second-operand
field.
Move Long
MVCL [RR]
o 8 12 15
The second operand is placed in the first-operand
location, provided overlapping of operand locations
does not affect the final contents of the first­
operand location. The remaining low-order byte
positions, if any, of the first-operand location are
filled with the padding character.
The Rt and R2 fields each specify an even-odd
pair of general registers and must designate an even­
numbered register; otherwise, a specification excep­
tion is recognized.
The location of the leftmost byte of the first oper­
and and second operand is designated by bits 8-31
of the general registers specified by the Rt and R2
fields, respectively. The number of bytes in the first­
operand and second-operand locations is specified
by bits 8-31 of general registers having addresses
R t + 1 and R2 + 1, respectively. Bit positions 0-7 of
register R2 + 1 contain the padding character. The
contents of bit positions 0-7 of registers R t, R2, and
R t + 1 are ignored.
Graphically, the contents of the registers just de­
scribed are as follows:
F irst-Operand Address
o 8 31
General Instructions 133

R1 + 1 F irst-Operand Length 0 8 31
R2 Second-Operand Address 0 8 31
R2 + 1 Second-Operand Length 0 8 31
The: movement starts at the high-order end of
both fields and proceeds to the right. The operation
is endt,d when the number of bytes specified by bit
positions 8-31 of register Rl + 1 have been moved
into the first-operand location. If the second oper­
and is shorter than the first operand, the remaining low-order bytes of the first operand are filled with
the padding character.
As part of the execution of the instruction, the
values of the two count fields are compared for the
setting of the condition code, and a check is made
for destructive overlap of the operands. Operands are said to overlap destructively when the first­
operand location is used as a source after data has
been moved into it, assuming the inspection for ov­
erlap is performed by the use of logical operand ad­
dresses. When the operands overlap destnlctively, no
movement takes place, and condition code 3 is set. Depending on whether the second operand wraps
around from location 16,777,215 to location 0, movement takes place in the following cases:
1. When the second operand does not wrap
around, movement is performed when the
high-order byte of the first operand coincides
with or is to the left of the high-order byte of
the second operand, or if the high-order byte of the first operand is to the right of the right­
most second-operand byte participating in the
operation.
2. \Vhen the second operand wraps around, move­
ment is performed when the high-order byte of the first operand coincides with or is to the left of the high-order byte of the second operand,
and if the high-order byte of the first operand
iis to the right of the rightmost second-operand
byte participating in the operation.
The rightmost second-operand byte is determined
by using the smaller of the first-operand and second­
operand counts.
When the count specified by bit positions 8-31 of registt,r Rl + 1 is zero, no movement takes place, and
the condition code is set to 0 or 1 to indicate the
relative values of the counts.
134 System/370 Principles of Operation The execution of the instruction is interruptible.
When an interruption occurs, the contents of regis­
ters Rl + 1 and R2+ 1 are decremented by the num­
ber of bytes moved, and the contents of register Rl
and R2 are incremented by the same number, so that
the instruction, when re-executed, resumes at the
point of interruption. The high-order byte of regis­
ters Rl and R2 is set to zero; the contents of the
high-order byte of registers Rl + 1 and R2+ 1 remain
unchanged; and the condition code is unpredictable.
If the operation is interrupted during padding, the
count field in register R2 + 1 is zero, the address in
register R2 is incremented by the original contents of
register R2 + 1, and registers R 1 and R 1 + 1 reflect the
extent of the padding operation.
When the first-operand location includes the loca­
tion of the instruction, the instruction may be re­
fetched from main storage and reinterpreted even in
the absence of an interruption during execution. The
exact point in the execution at which such a ref etch
occurs is unpredictable.
At the completion of the operation, the count in
register Rl + 1 is zero, and the address in register Rl
is incremented by the original value of the count in
register Rl + 1. The count in register R2+ 1 is decre­
mented by the number of bytes moved out of the
second-operand location, and the address in register
R2 is incremented by the same amount. The contents
of bit positions 0-7 of registers R 1 and R2 are set to
zero, including the case when one or both of the
original count values are zero or when condition
code 3 is set. The contents of bit positions 0-7 of
registers Rl + 1 and R2+ 1 remain unchanged.
When the count specified by bit positions 8-31 of
register Rl + 1 is zero, or condition code 3 is set, no
exceptions associated with operand access are recog­
nized. When the count specified by bit positions
8-31 of register R2+ 1 is zero, no access exceptions
for the second-operand location are recognized.
Similarly, when the second operand is larger than the
first operand, access exceptions are not recognized
for the part of the second-operand field that is in
excess of the first-operand field.
Resulting Condition Code:
o First-operand and second-operand counts are
equal
1 First-operand count is low
2 First-operand count is high
3 No movement performed because of destruc­
tive overlap Program Exceptions: Access (fetch, operand 2; store, operand 1)
Specification