R1 + 1 F irst-Operand Length 0 8 31
R2 Second-Operand Address 0 8 31
R2 + 1 Second-Operand Length 0 8 31
The: movement starts at the high-order end of
both fields and proceeds to the right. The operation
is endt,d when the number of bytes specified by bit
positions 8-31 of register Rl + 1 have been moved
into the first-operand location. If the second oper­
and is shorter than the first operand, the remaining low-order bytes of the first operand are filled with
the padding character.
As part of the execution of the instruction, the
values of the two count fields are compared for the
setting of the condition code, and a check is made
for destructive overlap of the operands. Operands are said to overlap destructively when the first­
operand location is used as a source after data has
been moved into it, assuming the inspection for ov­
erlap is performed by the use of logical operand ad­
dresses. When the operands overlap destnlctively, no
movement takes place, and condition code 3 is set. Depending on whether the second operand wraps
around from location 16,777,215 to location 0, movement takes place in the following cases:
1. When the second operand does not wrap
around, movement is performed when the
high-order byte of the first operand coincides
with or is to the left of the high-order byte of
the second operand, or if the high-order byte of the first operand is to the right of the right­
most second-operand byte participating in the
operation.
2. \Vhen the second operand wraps around, move­
ment is performed when the high-order byte of the first operand coincides with or is to the left of the high-order byte of the second operand,
and if the high-order byte of the first operand
iis to the right of the rightmost second-operand
byte participating in the operation.
The rightmost second-operand byte is determined
by using the smaller of the first-operand and second­
operand counts.
When the count specified by bit positions 8-31 of registt,r Rl + 1 is zero, no movement takes place, and
the condition code is set to 0 or 1 to indicate the
relative values of the counts.
134 System/370 Principles of Operation The execution of the instruction is interruptible.
When an interruption occurs, the contents of regis­
ters Rl + 1 and R2+ 1 are decremented by the num­
ber of bytes moved, and the contents of register Rl
and R2 are incremented by the same number, so that
the instruction, when re-executed, resumes at the
point of interruption. The high-order byte of regis­
ters Rl and R2 is set to zero; the contents of the
high-order byte of registers Rl + 1 and R2+ 1 remain
unchanged; and the condition code is unpredictable.
If the operation is interrupted during padding, the
count field in register R2 + 1 is zero, the address in
register R2 is incremented by the original contents of
register R2 + 1, and registers R 1 and R 1 + 1 reflect the
extent of the padding operation.
When the first-operand location includes the loca­
tion of the instruction, the instruction may be re­
fetched from main storage and reinterpreted even in
the absence of an interruption during execution. The
exact point in the execution at which such a ref etch
occurs is unpredictable.
At the completion of the operation, the count in
register Rl + 1 is zero, and the address in register Rl
is incremented by the original value of the count in
register Rl + 1. The count in register R2+ 1 is decre­
mented by the number of bytes moved out of the
second-operand location, and the address in register
R2 is incremented by the same amount. The contents
of bit positions 0-7 of registers R 1 and R2 are set to
zero, including the case when one or both of the
original count values are zero or when condition
code 3 is set. The contents of bit positions 0-7 of
registers Rl + 1 and R2+ 1 remain unchanged.
When the count specified by bit positions 8-31 of
register Rl + 1 is zero, or condition code 3 is set, no
exceptions associated with operand access are recog­
nized. When the count specified by bit positions
8-31 of register R2+ 1 is zero, no access exceptions
for the second-operand location are recognized.
Similarly, when the second operand is larger than the
first operand, access exceptions are not recognized
for the part of the second-operand field that is in
excess of the first-operand field.
Resulting Condition Code:
o First-operand and second-operand counts are
equal
1 First-operand count is low
2 First-operand count is high
3 No movement performed because of destruc­
tive overlap Program Exceptions: Access (fetch, operand 2; store, operand 1)
Specification

PTogranrnmdng The instruction MOVE LONG can be used for clear­
ing storage. Clearing can be accomplished by setting
the padding character to zero and the second oper­
:and count to zero.
When the first-operand count is zero, the opera­
tion consists in setting the condition code and setting
the high-order bytes of registers Rl and R2 to zero.
When the contents of the R 1 and R2 fields are the
same, the operation proceeds the same way as when
two distinct pairs of registers having the same con­
tents are specified. Condition code 0 is set, and pro­
tection and addressing exceptions are indicated when
called for by the operand designation.
Since the execution of MOVE LONG is interrup­
tible, the instruction cannot be used for situations
where the program must rely on uninterrupted exe­
cution of the instruction or on the interval timer not
being updated during the execution of the instruc­
tion. Similarly, the program should normally not let
the first operand of MOVE LONG include the loca­
tion of the instruction since the new contents of the
location may be interpreted for a resumption after
an interruption, or if the instruction is ref etched
without an interruption.
Special precautions must be taken if MOVE LONG is made the subject of EXECUTE. See the
programming notes under EXECUTE.
When the stop key is activated during the execu­
tion of MOVE LONG or COMPARE LOGICAL LONG, the CPU enters the stopped state at the
completion of the execution of the next unit of oper­
ation. Similarly, in the instruction-step mode, only a
unit of operation is performed. The amount of data
processed in a unit of operation depends on the
model and may depend on the particular condition
that causes the execution of the instruction to be
interrupted.
Move Numerics
MVN [SS] L--D_1 -L---.,L --1..--1· Bl--J........{I o 8 16 20 32 36 47
The low-order four bits of each byte in the second­
operand field, the numerics, are placed in the low­
order bit positions of the corresponding bytes in the
first-operand field. The high-order four bits of each
byte in the first-operand field remain unchanged.
Each operand field is processed left to right.
When the operands overlap, the result is obtained as
if the operands were processed one byte at a time
and each result byte were stored immediately after
the necessary operand byte is fetched.
Condition Code:
The code remains unchanged.
Program Exceptions: Access (fetch, operand 2; fetch and store, oper­
and 1)
Programming The execution of MVN consists in fetching the low- larder four bits of each byte in the first-operand
field, and subsequently storing the updated value of
the byte. These fetch and store accesses to a partic­
ular byte do not necessarily occur one immediately
after the other.
Move With Offset MVO [SS1
F1 I o 8 12 16 20 32 36 47
The second operand is placed to the left of and adja· cent to the low-order four bits of the first operand.
The low-order four bits of the first operand are
attached as low-order bits to the second operand,
the second operand bits are offset by four bit posi­
tions, and the result is placed in the first-operand
location. The first-operand and second-operand
bytes are not checked for valid codes.
The result is obtained as if the fields were pro­
cessed right to left. If necessary, the second operand
is extended with high-order zeros. If the first­
operand field is too short to contain all bytes of the
second operand, the remaining information is ig­
nored.
When the operands overlap, the result is obtained
as if the operands were processed one byte at a time
and each result byte were stored immediately after
the necessary operand bytes are fetched. The high­
order digit of each second-operand byte remains
available for the next result bytc and is not rc­
fetched.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2; fetch and store, oper­
and 1)
General Instructions 135