Shift Right Double SRDA The double-length integer part of the first operand is
shifted right the number of places specified by the
second-operand address. Bits 12-15 of the instruc
tion are ignored.
The R 1 field of the instruction specifies an even
odd pair of registers and must designate an even register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
addressis ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par
ticipate in the shift in the same manner as the other
integer bits. The low-order bits are shifted out with
out inspection and are lost. Bits equal to the sign are
supplied to the vacated positions of the registers.Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
Specification
Shiftllight Double Logical SRDL Rl,D2(B2) [RS] The double-length first operand is shifted right the
number of bits specified by the second-operand ad
dress. Bits 12-15 of the instruction are ignored.
The Rl field of the instruction specifies an even
odd pair of registers and must designate an even
numbered register. When Rl is odd, a specification
exception is recognized.140 System/370 Principles of Operation The second-operand address is not used to ad
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. Low-order bits are shifted out of the odd
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Right Single
8A
o 8 12 1620 31
The integer part of the first operand is shifted right
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to ad
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
right shift. Bits equal to the sign are supplied to the
vacated high-order bit positions. Low-order bits are
shifted out without inspection and are lost.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
ProgramExceptions: None
Programming Note
A right shift of one bit position is equivalent to divi
sion by two with rounding downward. When an even
number is shifted right one position, the value of the
field is that obtained by dividing the value by 2.
When an odd number is shifted right one position,
the value of the field is that obtained by dividing the
next lower number by two. For example, +5 shifted
right by one bit position yields + 2, whereas -5 yields
-3.
shifted right the number of places specified by the
second-operand address. Bits 12-15 of the instruc
tion are ignored.
The R 1 field of the instruction specifies an even
odd pair of registers and must designate an even
exception is recognized.
The second-operand address is not used to ad
dress
of bit positions to be shifted. The remainder of the
address
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par
ticipate in the shift in the same manner as the other
integer bits. The low-order bits are shifted out with
out inspection and are lost. Bits equal to the sign are
supplied to the vacated positions of the registers.
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
Specification
Shift
number of bits specified by the second-operand ad
dress. Bits 12-15 of the instruction are ignored.
The Rl field of the instruction specifies an even
odd pair of registers and must designate an even
numbered register. When Rl is odd, a specification
exception is recognized.
dress
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. Low-order bits are shifted out of the odd
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Right Single
8A
o 8 12 16
The integer part of the first operand is shifted right
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to ad
dress
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
right shift. Bits equal to the sign are supplied to the
vacated high-order bit positions. Low-order bits are
shifted out without inspection and are lost.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program
Programming Note
A right shift of one bit position is equivalent to divi
sion by two with rounding downward. When an even
number is shifted right one position, the value of the
field is that obtained by dividing the value by 2.
When an odd number is shifted right one position,
the value of the field is that obtained by dividing the
next lower number by two. For example, +5 shifted
right by one bit position yields + 2, whereas -5 yields
-3.