Program Exceptions:
Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of AU and AW only)
Specification
Exponent Overflow
Significance
Compare
CER Rl,R2
[RR, Short Operands]
o 8 12 15
CE Rl,D2(X2,B2)
[RX, Short Operands]
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 -
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of CE and CD only)
Specification
Programming Note
Numbers with zero fractions compare equal even
when they differ in sign or characteristic.
Divide
DER Rl,R2
79 I R, I X
2 I B2 D2 I [RR, Short Operands 1 [ 3D I R, I R, CDR Rl,R2
[RR, Long Operands]
29
o 8 12 15
CD Rl,D2(X2,B2)
[RX, Long Operands]
o 8 12 15
DE Rl,D2(X2,B2)
[RX, Short Operands]
7D
o 8 12 16 20 31
DDR Rl,R2 I 69 I R, I x
2 I B2 D2 I [RR, Long Operands 1 I 2D I R, I R2
The first operand is compared with the second op­
erand, and the condition code is set to indicate the
result.
Comparison is algebraic, taking into account the
sign, fraction, and exponent of each number. An
equality is established by following the rules for nor­
malized floating-point subtraction. When the inter­
mediate sum, including the guard digit, is zero, the
operands are equal. An exponent inequality is not
decisive for magnitude determination since the frac­
tions may have different numbers of leading zeros.
Neither operand is changed as a result of the opera­
tion.
An exponent-overflow, exponent-underflow, or
significance exception cannot occur.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
o 8 12 15"
DD Rl,D2(X2,B2)
[RX, Long Operands]
6D
o 8 12 16 20 The first operand (the dividend) is divided by the
second operand (the divisor) and replaced by the
normalized quotient. No remainder is preserved.
31
Floating-point division consists in characteristic
subtraction and fraction division. The operands are
prenormalized, and the difference between the divi­
dend and divisor characteristics of the normalized
operands, plus 64, is used as the characteristic of the
intermediate quotient.
All dividend and divisor fraction digits participate
in forming the fraction of the quotient. Postnormal-
Floating-Point Instructions 163

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22·0498 izing the intennediate quotient is never necessary,
but a right-shift of one digit position may be called
for. The intennediate-quotient characteristic is ad­
justed for the shift. The intennediate-quotient frac­
tion is subsequently truncated to the proper result­
fraction length.
The sign of the quotient is determined by the
rules of algebra, unless the quotient is made a true
zero, in which case the sign is made plus.
An exponent-overflow exception is recognized
when the final-quotient characteristic exceeds 127
and the fraction is not zero. The operation is com­
pleted, and a program interruption occurs. The result
is normalized, the sign and fraction remain correct,
and the characteristic is 128 less than the correct
value.
An exponent-underflow exception exists when the
characteristic of the nonnalized quotient is less than
zero and the fraction is not zero. If the exponent­
underflow mask bit is one, a program interruption
occurs. The result is nonnalized, its sign and fraction
remain correct, and the characteristic is made 128
larger than the correct value. If the exponent under­
flow mask bit is zero, a program interruption does
not take place; instead, the operation is completed
by making the quotient a true zero.
Exponent underflow is not signaled when an op­
erand characteristic becomes less than zero during
prenonnalization or the intennediate-quotient char­
acteristic is less than zero, but the final quotient can
be expressed without encountering exponent under­
flow.
A floating-point divide exception is recognized
when the divisor fraction is zero. The operation is
suppressed, and a program interruption for floating­
point divide occurs.
When the dividend fraction is zero, the quotient is
made a true zero, and a possible exponent overflow
or exponent underflow is not recognized. A division
of zero by zero, however, causes the operation to be suppressed and an interruption for floating-point
divide to occur. The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized. Cond.rtion Code:
The code remains unchanged. PrognfJm Exceptiom: Operation (if the floating-point feature is not
installed) Aceess (fetch, operand 2 of DD and DE only) Specification Exponent Overflow
164 System/370 Principles of Operation Exponent Underflow
Floating-Point Divide
Halve
HER Rl,R2
[RR, Short Operands]
34
o 8 12 15
HDR Rl,R2
[RR, Long Operands]
24
o 8 12 15
The second operand is divided by 2, and the normal­
ized quotient is placed in the first-operand location.
The fraction of the second operand is shifted right
one bit position, placing the contents of the low­
order bit position· into the high-order bit position of
the guard digit and introducing a zero into the high­
order bit position of the fraction. The intennediate
result is subsequently normalized, and the normal­
ized quotient is placed in the first-operand location.
The guard digit participates in the normalization.
The sign of the quotient is the same as that of the
second operand, unless the quotient is made a true
zero, in which case the sign is made plus.
An exponent-underflow exception exists when the
characteristic of the nonnalized quotient is less than
zero and the fraction is not zero. If the exponent­
underflow mask bit is one, a program interruption
occurs. The result is nonnalized, its sign and fraction
remain correct, and the characteristic is made 128
larger than the correct value. If the exponent under­
flow mask bit is zero, program interruption does not
take place; instead, the operation is completed by
making the quotient a true zero.
When the fraction of the second operand is zero,
the result is made a true zero, and no exceptions are
recognized.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Specification
Exponent Underflow