Name
ADD NORMALIZED (extended)
ADD NORMALIZED (long)
ADD NORMALIZED (long)
ADD NORMALIZED (short)
ADD NORMALIZED (short)
ADD UNNORMALIZED (long) ADD UN NORMALIZED (long)
ADD UN NORMALIZED (short)
ADD UNNORMALIZED (short) COMPAR E (long) COMPARE (long) COMPARE (short) COMPARE (short) DIVI DE (long) DIVIDE (long) DI VI DE (short) DIVIDE (short)
HALVE (long) HALVE (short)
LOAD (long)
LOAD (long) LOAD (short)
LOAD (short)
LOAD AND TEST (long)
LOAD AND TEST (short)
LOAD COMPLEMENT (long)
LOAD COMPLEMENT (short)
LOAD NEGATIVE (long)
LOAD NEGATIVE (short)
LOAD POSITIVE (long) LOAD POSITIVE (short)
LOAD ROUNDED (extended to long)
LOAD ROUNDED (long to short) MULTIPLY (extended) MULTIPLY (long) MULTIPLY (long)
MU L TI PL Y (long to extended) MULTIPLY (long to extended)
MUL TIPL Y (short to long) MULTIPLY (short to long) STORE (long) STORE (short) SUBTRACT NORMALIZED (extended) SUBTRACT NORMALIZED (long) SUBTRACT NORMALIZED (long) SUBTRACT NORMALIZED (short) SUBTRACT NORMALIZED (short) SUBTRACT UNNORMALIZED (long) SUBTRACT UNNORMALIZED (long) SUBTRACT UNNORMALIZED (short) SUBTRACT UNNORMALIZED (short)
Explanation:
A Access exceptions C Condition code is set
E Exponent-overflow exception
FK Floating-point divide exception
FP Floating-point feature LS Significance exception
Floating-Point-Instruction Summary
Mnemonic
AXR
ADR
AD
AER
AE
AWR
AW
AUR
AU CDR CD CER CE DDR
DD
DER
DE
HDR
HER
LDR
RR C RR C RX C RR C RX C RR C RX C RR C RX C RR C RX C RR C RX C RR
RX
RR
RX
RR
RR
RR
LD RX
LER RR
LE RX
LTDR RR C LTER RR C LCDR LCER LNDR
LNER
LPDR
RR C RR C RR C RR C RR C LPER RR C LRDR RR
LRER RR
MXR RR
MDR RR
MD RX
MXDR RR
MXD RX
MER RR
ME RX STD STE SXR SDR SD SER SE SWR SW SUR SU RX
RX
RR C RR C RX C RR C RX C RR C RX C RR C RX C XP
FP
FP A
FP
FP A
FP
FP A
FP
FP A
FP
FP A
FP
FP A
FP
FP A
FP
FP A
FP
FP
FP
FP A
FP
FP A
FP
FP
FP
FP
FP
FP
FP
FP
XP
XP
XP
FP
FP A
XP
XP A
FP
FP A
FP A
FP A
XP
FP
FP A
FP
FP A
FP
FP A
FP
FP A
Characteristics SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP SP U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U t RR RR instruction format RX RX instruction format i SP Specification exception\ ST PER storage alteratio'n";vent E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
U
Exponent underflow exception
FK
FK
FK
FK
XP Extended-precision floating-point feature LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS ST ST Code 36
2A
6A
3A
7A
2E
6E
3E
7E
29
69
39
79
2D
6D
3D
7D
24
34
28
68
38
78
22
32
23
33
21
31 20 30 25
35
26 2C 6C 27
67 3C 7C 60 70 37
2B
6B
3B
7B
2F
6F
3F
7F
Floating-Point Instructions 161
underflow mask bit is one, the operation is complet­
ed by making the characteristic 128 larger than the
correct value. The result is normalized, and the sign
and fraction remain correct. A program interruption
for exponent underflow then takes place. When ex­
ponent underflow occurs and the exponent­
underflow mask bit is zero, a program interruption
does not take place; instead, the operation is com­
pleted by making the result a true zero. For AXR,
exponent underflow is not recognized when the low­
order characteristic is less than zero, but the high­
order characteristic is zero or above.
A significance exception exists when the
intermediate-sum fraction, including the guard digit,
is zero. If the significance mask bit is one, the
intermediate-sum characteristic remains unchanged
and becomes the characteristic of the ,result. No nor­
malization occurs, and a program interruption for
significance takes place. If the significance mask bit
is zero, the program interruption does not occur;
instead, the result is made a true zero.
The Rl field for AER, AE, ADR, and AD" and
the R2 field for AER and ADR must designate regis­
ter 0,2,4, or 6. The Rl and R2 fields for AXR must
designate register 0 or 4.
Otherwise, a specification
exception is recognized.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed, or, for AXR, if the extended­ preeision floating-point feature is not installed)
Access (fetch, operand 2 of AE and AD only) Specification Exponent Overflow
Exponent Underflow
Significance
Programming Note
Interchanging the two operands in a floating-point
addition does not affect the value of the sum.
162 System/370 Principles of Operation Add Unnormalized AUR Rl,R2
[RR, Short Operands]
o 8 12 15 AU [RX, Short Operands]
7E
o 8 12 16 20 AWR Rl,R2
[RR, Long Operands]
o 8 12 15
AW Rl,D2(X2,B2)
[RX, Long Operands]
6E I R, I x
2 I 8
2 D2 0 8 12 16 20 The second operand is added to the first operand,
and the unnormalized sum is placed in the first­
operand location.
31
31
The execution of ADD UNNORMALIZED is
identical to that of ADD NORMALIZED, except
that, after the addition, the intermediate-sum frac­
tion is truncated to the proper result-fraction length
without performing normalization. Leading zeros are
not eliminated in the result fraction, exponent under­
flow cannot occur, and the guard digit does not par­
ticipate in the recognition of significance exception.
A significance exception is recognized when the
intermediate-sum fraction, not including the guard
digit, is zero.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Previous Page Next Page