specifies that the entire contents of a checking block
are to be replaced, validation mayor may not occur, depending on the operation and the model. Storage
validation during the IPL input operations follows
the same rules as for normal input operations.
Programmed Validation of Storage
Execution of the instruction MOVE (MVC) or MOVE LONG (MVCL) validates the main-storage
area containing the first operand when the following
conditions are satisfied: • The first-operand field and second-operand
field participating in the operation do not over­
lap. • The first-operand field starts on a boundary of a
checking block and is an integral number of
checking blocks in length. • For MVCL, the second-operand field, if nonze­
ro in length, starts on a boundary of a checking
block and, if it is shorter than the first-operand
field, is an integral number of checking blocks
in length.
An interruption or stopping of the CPU during
execution of MVCL does not affect the validation
function performed.
Handling of Invalid CBC in Keys in
Storage
Depending on the model, each key in storage may
consist of a single checking block, or the protection
bits and the change and reference bits may be in
separate checking blocks. Invalid CBC on the key in
storage is ignored in storing or fetching with a zero
protection key. References to main storage to which
protection does not apply are treated as if a protec­
tion key of zero is used for the reference. This in­
cludes such references as channel references during
the IPL procedure, implicit references such as in
timer updating and interruption action, and OAT table accesses. The key in storage is validated by
SET STORAGE KEY.
The table "Handling of Invalid CBC in Keys in
Storage" describes the action taken when the key in
storage has invalid CBC.
Handling of Invalid CBC in Registers
During a machine-check interruption, the contents
of the general, floating-point, and control registers,
and of the CPU timer and clock comparator if they
are installed, are stored at fixed locations in main
storage. Invalid CBC detected during this operation
does not result in additional machine-check­
interruption conditions; instead, the accuracy of the
information stored is indicated by the appropriate
setting of the validity bits in the machine-check­
interruption code. On some models, registers with
invalid CBC will be automatically validated during
the interruption. On other models, programmed vali­
dation is required. The TOO clock and the prefix
register are not stored during the machine-check
interruption and are not validated. On those models in which registers are not auto­
matically validated as part of the machine-check
interruption, a register with invalid CBC will not
cause a machine-check interruption condition unless
the contents of the register are actually used. In
these models, each register may consist of one or
more checking blocks, but multiple registers are not
included in a single checking block. When only a
portion of a register is accessed, invalid CBC in the
unused portion of the same register may cause a
machine-check interruption condition. For example,
invalid CBC in the right half of a long operand of a
floating-point register may cause a machine-check
interruption condition if a LOAD (LE) operation
attempts to replace the left half, or short form, of
the register.
Invalid CBC associated with the check-stop con­
trol bit (control register 14, bit 0) and with the asyn­ 'chronous fixed-logout control bit (control register
14, bit 9) will cause the CPU either to immediately
enter check-stop state or to assume that bits 0 and 9
have their initialized values of one and zero, respcc­
tively.
Invalid CBC associated with the prefix register
cannot be safely reported by the machine-check
interruption, since the interruption itself requires
that the prefix value be applied to convcrt real ad­
dresses to the corresponding absolute addresses.
When the check-stop control bit (control register 14,
bit 0) is one, invalid CBC in the prefix register caus­
es the CPU to immediately enter the check-stop
state. When the check-stop control bit is zero, inval­
id CBC in the prefix register either may cause the CPU to enter the check-stop state or may generate a
system damage condition, depending on the model.
Validation of Registers On those models which do not validate registers
during a machine-check interruption, the following
instructions will cause validation of a register, pro­
vided the information in the register is not used be­
fore the register is validated. Other instructions,
although they replace the entire contents of a regis­
ter, do not necessarily cause validation.
General registers are validated by BRANCH
AND LINK (BAL, BALR), LOAD (LR), and LOAD ADDRESS (LA). LOAD (L) and LOAD MULTIPLE (LM) validate if the operand is on a
Machine-Check Handling 173

Type of IReference Set Storage Key I nsert Storage Key
Reset Reference Bit
Fetch, Nonzero Protection Key
Store, Nonzero Protection Key
Fetch, Ze'ro Protection Key
Store, Zem Protection Key
Explanation:
For Protection Bits Complete; validate. PO; preserve. PO or complete;
preserve. MC; preserve. MC 1
; preserve.
Complete; preserve.
Complete; preserve.
Action Taken on Invalid CBC For Reference and Change Bits
Complete; validate. PO in EC mode, PO or
complete in BC mode;
preserve. PO; preserve. MC or complete;
preserve. MC or complete;
preserve or correct. Complete; preserve.
Complete; preserve or
correct.
For Protection Bits and
Reference and Change Bits
Complete; validate. PO; preserve. PO; preserve. MC; preserve.
Me
1
; preserve. Complete; preserve.
Complete; preserve
2
.
Complete The condition does not cause termination of the execution of the instruction and, unless an unrelated
condition prohibits it, the execution of the instruction is completed, ignoring the error condition.
No machine-check damage conditions are generated, but recovery-report conditions may be generated. PO A machine-check instruction processing damage or system damage condition is recognized. MC Same as PO for CPU references, but an I/O reference may result in the following combinations of I/O interruption and machine-check interruption.
a) Channel control check and no machine-check interruption.
Validate
b) Channel control check and a recovery report.
cl External damage and no I/O interruption.
d) System damage and no I/O interruption.
The entire key is set to the new value with valid CBC. Preserve The contents of the entire checking block having invalid CBC are left unchanged. Correct The reference and change bits are set to one with valid CBC. The contents of the main-storage location are not changed.
2 On models with separate checking blocks for protection bits and for change and reference bits; the protection
bits are preserved, and the change and reference bits may be corrected or preserved.
Handling of Invalid CBC in Keys in Storage word boundary, and LOAD HALFWORD (LH)
validates if the operand is on a half word boundary.
Floating-point registers are validated by LOAD (LDR) and, if the operand is on a double word
boundary, by LOAD (LD).
Control registers may be validated either singly or
in groups by using the instruction LOAD CON­ TROL (LCTL).
The CPU timer and clock comparator arc validat­
ed by SET CPU TIMER (SPT) and SET CLOCK COMPARATOR (SCKC), respectively.
The TOD clock is validated by SET CLOCK (SCK) if the TOD clock security switch is in the
enable-set position.
174 System/370 Principles of Operation Programming Note
To provide for a model-independent machine-check
first-level-interruption handler, registers must be
validated before they are used. Examples: START I/O, SET SYSTEM MASK, and SET CLOCK should not be executed until control register 0 (containing block-multiplexing control, SSM­
suppression control, and TOD clock synchronization
control bits), is validated. MONITOR CALL should
not be issued until control register 8, containing the
monitor class masks, is validated. Extended channel
masks, external masks, and machine-check controls
should be validated before the associated interrup­
tions are allowed. The clock comparator and CPU timer should be validated before clock-comparator
and CPU-timer interruptions are allowed.