tion; the interruption is taken after the execution of
the current instruction has come to its normal ending
and the associated program or supervisor-call inter­
ruption, if any, has been taken. No program or
supervisor-call interruptions are If the
repressible machine-check condition occurs during
the execution of a system function such as a timer
update, the machine-check interruption takes place
after the system function has been completed.
A machine-check interruption due to an exigent
machine-check condition can occur only when PSW bit 13 is one. The interruption terminates the execu­
tion of the current instruction and may eliminate the
program and supervisor-call interruptions, if any,
that would have occurred as a result of continuing
execution of the instruction. Proper execution of the
interruption steps, including the storing of the old PSW and diagnostic information, depends on the
nature of the malfunction. When an exigent
machine-check condition occurs during the execu­
tion of a system function, such as a timer update, the
sequence is not necessarily completed.
When PSW bit 13 is zero and an exigent machine­
check condition is generated, subsequent action de­
pends on the state of the check-stop control bit, bit
o of control register 14. When the check-stop con­
trol bit is zero, the machine-check condition is held
pending, and an attempt is made to complete the
execution of the current instruction and to proceed
with the next sequential instruction. When the
check-stop control bit is one, processing stops imme­
diately, and the CPU enters the check-stop state.
Depending on the model and the severity of the er­
ror, the CPU may enter the check-stop state even
when the check-stop control bit is zero.
Similarly, if, during the execution of an interrup­
tion due to one exigent machine-check condition,
another exigent machine-check condition is detected,
subsequent action depends on the state of the check­
stop control bit. If the check-stop control bit is one,
the CPU enters the check-stop state; if the bit is
zero, an attempt is made to proceed with the condi­
tion held pending for subsequent interruption. If an
exigent machine-check condition is detected during
an interruption due to a repressible machine-check
condition, system damage is also reported.
Exigent machine-check conditions held pending
while the check-stop control bit is zero remain pend­
ing and do not cause the CPU to enter the check­
stop state if the check-stop control bit is subsequent­
ly set to one.
If a repressible machine-check condition is detect­
ed with the CPU disabled for the associated machine-check interruption condition, the condition
is held pending. If a system-recovery condition is
176 System/370 Principles of Operation detected during the execution of the interruption
procedure due to a previous machine-check condi­
tion, the system-recovery condition may be com­
bined with the other conditions, discarded, or held
pending. The CPU never enters the check-stop state
because of a repressible machine-check condition. Only one machine-check interruption condition is
held pending for each subclass, regardless of the
number of conditions that may have been detected.
Machine-check interruptions can be initiated only
by an interruption condition in a subclass for which
the CPU is enabled. Conditions in other subclasses
which are pending may also be indicated in the same
interruption even though the CPU is not enabled for
those subclasses. All conditions which are indicated
are then cleared.
Machine-check interruption conditions are han­
dled in the same manner in both the running and
wait states. In the wait state, a machine-check inter­
ruption condition for which the CPU is enabled
causes an immediate interruption.
Machine checks which occur while processing is
in the instruction-step mode are handled in the same
manner as in process mode; that is, normal recovery,
logout, and machine-check interruptions occur when
allowed. Machine checks occurring during a manual
operation such as system reset, set Ie, or store, may
generate a system-recovery condition. If damage has
been caused which is not corrected or not circum­
vented, the CPU enters the check-stop state.
Every reasonable attempt is made to limit the
side-effects of any machine-check condition and the
associated interruption. Normally, I/O and external
interruptions, as well as the progress of I/O data
transfer and the updating of the timer, remain unaf­
fected. The malfunction, however, may affect these
activities, and, if the currently active PSW has bit 13
set to one, the machine-check interruption may ter­
minate the process of switching PSW s that is due to
another type of interruption. In these cases, system
damage will be indicated.
Point of Interruption
Because of the checkpoint capability in models with
machine retry, the interruption resulting from an
exigent machine-check interruption condition may
indicate a point in the recovery cycle which is prior
to the error. Additionally, the model may have some
choice as to which point in the recovery cycle the
interruption will indicate, and, in some cases, the
status which can be marked as valid depends on the
point chosen.
The point in the processing which is indicated by
the interruption and used as a reference point by the
machine to determine and the validity of the

status stored is referred to as the "point of interrup­ tion." Only certain points in the processing may be used
as a point of interruption. For repressible machine
checks the point of interruption must be after one
unit of operation is completed, including the associ­
ated program or supervisor-call interruption, if appli­
cable, and before the next unit of operation is begun.
Exigent machine-check conditions which are de­
layed (disallowed and presented later when allowed)
can occur only at the same points of interruption as
repressible machine-check conditions. When an exi­
gent machine-check condition is not delayed, the
point of interruption may also be after the unit of
operation is completed but before the associated
program or supervisor-call interruption occurs. In
this case, a valid PSW is defined as that which would
have been stored in the old PSW for the program or
supervisor-call interruption. Even though all status
may be indicated as valid, damage has occurred be­
cause the associated interruption is lost.
Programming Note
When an exigent machine-check condition occurs,
the point of interruption which is chosen affects the
amount of damage which must be indicated. An at­
tempt is made, when possible, to choose a point of
interruption which permits the minimum indication
of damage. In general, the preference is the interrup­
tion point immediately preceding the error. When a
point of interruption is chosen which is after an as­
sociated program or supervisor-call interruption, the
damage has not been isolated to a particular pro­
gram, and system damage is indicated.
When all the status information stored as a result
of an exigent machine-check condition does not
reflect the same point, an attempt is made when
possible to choose the point of interruption so that
the instruction address which is stored in the
machine-check old PSW is valid. Alachine-Check Logout
The storing of model-dependent information in main
storage as a result of a machine check is referred to
as a machine-check logout. Machine-check logouts
are of four different types: synchronous fixed logout,
asynchronous fixed logout, synchronous machine­
check extended logout, and asynchronous machine­
check extended logout.
When a machine-check logout occurs during the
machine-check interruption it is called "h "If h' sync ronous. a mac me-check logout occurs
without a machine-check interruption, or if the log­
out and the interruption are separated by instruction
processing or by instruction retry, then the logout is
called "asynchronous." Machine-cheek-logout information can be placed
in either or both of two areas. One area, the 96-byte
area starting at location 256, is called the "fixed­ logout area." Additionally, a machine-check
extended-logout area (MCEL) is defined. The start­
ing location of the MCEL area is specified by the
contents of control register 15. The existence and
length of the machine-check extended logout are
model-dependent.
To preserve the initial machine-check conditions,
some models perform an asynchronous logout before
invoking automatic CPU recovery action. Depending
on the model, logout may occur before recovery,
after recovery, or at both times. If logout occurs at
both times it may be into the same portion or two
different portions of the logout area. Alachine-Check Extended Interruption
Information
The machine-check extended interruption informa­
tion consists of seven fields, which are stored at
machine-check interruption time. Each of these
fields has a validity bit associated with it in the
machine-check interruption code. If for any reason
the machine cannot store one of these fields or can­
not store the field validly, the associated validity bit
is set to zero.
Timing Facilities: When the system-timing facilities
are present, any machine-check interruption causes
the contents of the clock comparator and CPU timer
to be placed in storage as part of the machine-check
extended interruption information. The contents of
the clock comparator are stored in the doubleword
starting at location 224. The contents of the CPU timer are placed in the double word starting at loca­
tion 216.
Fai/ing-Storage Address: When a storage error un­
corrected, storage error corrected, or key in storage
error uncorrected has been indicated, the failing­
storage address is stored in bits 8-31 of the word at
location 248. Bits 0-7 of the word are set to zeros.
In the case of storage errors, the failing-storage ad­
dress may point to any byte within the checking
block. For key in storage error uncorrected, the
failing-storage address may point to any address
within the 2,048-byte block of storage associated
with the key in storage that is in error. When an
error is detected in more than one location before
the interruption, the failing-storage address may
point to any of the failing locations. The address
stored is an absolute address; that is, the value
Machine-Check Handling 177