placement provides for relative addressing of up to 4,095 bytes beyond the location designated by the
base address. In array-type calculations, the dis
placement can be used to specify one of many itemsassociated: with an element. In the processing of
records, the displacement can be used to identify
items within a record.
In forming the address, the base address and in
dex are treated as unsigned 24-bit positive binary
integers. The displacement is similarly treated as a
12-bit positive binary integer, and 12 high-order
zeros are appended. The three are added as 24-bit
binary numbers, ignoring overflow. The sumis al
ways 24 bits long. The bits of the generated address
are numbered 8-31, corresponding to the numbering
of thebas'e-address and index bits in the general
register.
A zero in any of the X2, Bl, or B2 fields indicates
the absenee of the corresponding address compo
nent. For the absent component, a zero is used in
forming the address, regardless of the contents of
general register0. A displacement of zero has no
special significance.
An instruction can designate the same general
register both for address computation and as the
location of an operand. Address computation is
completedl prior to the execution of the operation.
Unless otherwise indicated in the individual in
struction definition, the computed operand address
designates an operand in main storage. When a
main-storage operand is designated, the address des
ignates the leftmost byte of the operand. For
branching instructions, the second-operand address
is used as the branch address. For shifting instruc
tions, the second-operand address is not used as an
address but specifies the shift amount.Prograr.n Status Word
The program status word (PSW) is 64 bits in length
and contains the information required for proper
program execution. ThePSW includes the instruc
tion address, condition code, and other fields. In
general, thePSW is used to control instruction se
quencing and to hold and indicate the status of the
system in relation to the program currently being
executed. The active or controllingPSW is called the cun-ent PSW. By storing the current PSW during an
interruption, the status of the CPU can be preserved
for subsequent inspection. By loading a newPSW or
part of aPSW, the state of the CPU can be initial
ized or changed.
22 System/370 Principles of Operation
Instruction Execution
In program execution, the instruction is fetched from
the location designated by the instruction address in
the currentPSW. The instruction address is then
increased by the number of bytes in the instruction
in order to address the next instruction in sequence.
The instruction is then executed, and the same steps
are repeated using the new value of the instruction
address.
Branching
The normal sequential execution of instructions may
be changed by the use of the branching instructions
in order to perform subroutine linkage, decision
making, and loop control.
Subroutine linkage is provided by the BRANCH
AND LINK instructions, which permit not only the
introduction of a new instruction address but also
the preservation of the return address and associated
information.
Facilities for decision making are provided by the
BRANCHON CONDITION instruction. This in
struction inspects a two-bit condition code that re
flects the result of a majority of the arithmetic, logi
cal, andI/O operations. Each of these operations
can set the code in anyone of four states, and the
instruction BRANCHON CONDITION can specify
any selection of these four states as the criterion for
branching. For example, the condition code reflects
such conditions as nonzero, first operand high,
equal, overflow, channel busy, and zero.Once set,
the condition code remains unchanged until modified
by an instruction that causes a different condition
code to be set.
The two bits of the condition code provide for
four possible condition code settings:0, 1, 2, and 3.
The specific meaning of any setting depends on the
operation that sets the condition code.
Loop control can be performed by the use of
BRANCHON CONDITION to test the outcome of
address arithmetic and c0unting operations. For
some particularly frequent combinations of arithme
tic and tests, the instructions BRANCHON COUNT and BRANCH ON INDEX are provided.
These branches, being specialized, provide increased
performance for these tasks.
Interruptions
The interruption system permits the CPU to change
state as a result of conditions external to the system,
in input/output(I/O) units, or in the CPU itself. Six classes of interruption conditions are possible: ma
chine check, supervisor call, program, external,I/O, and restart.
base address. In array-type calculations, the dis
placement can be used to specify one of many items
records, the displacement can be used to identify
items within a record.
In forming the address, the base address and in
dex are treated as unsigned 24-bit positive binary
integers. The displacement is similarly treated as a
12-bit positive binary integer, and 12 high-order
zeros are appended. The three are added as 24-bit
binary numbers, ignoring overflow. The sum
ways 24 bits long. The bits of the generated address
are numbered 8-31, corresponding to the numbering
of the
register.
A zero in any of the X2, Bl, or B2 fields indicates
the absenee of the corresponding address compo
nent. For the absent component, a zero is used in
forming the address, regardless of the contents of
general register
special significance.
An instruction can designate the same general
register both for address computation and as the
location of an operand. Address computation is
completedl prior to the execution of the operation.
Unless otherwise indicated in the individual in
struction definition, the computed operand address
designates an operand in main storage. When a
main-storage operand is designated, the address des
ignates the leftmost byte of the operand. For
branching instructions, the second-operand address
is used as the branch address. For shifting instruc
tions, the second-operand address is not used as an
address but specifies the shift amount.
The program status word (PSW) is 64 bits in length
and contains the information required for proper
program execution. The
tion address, condition code, and other fields. In
general, the
quencing and to hold and indicate the status of the
system in relation to the program currently being
executed. The active or controlling
interruption, the status of the CPU can be preserved
for subsequent inspection. By loading a new
part of a
ized or changed.
22 System/370 Principles of Operation
Instruction Execution
In program execution, the instruction is fetched from
the location designated by the instruction address in
the current
increased by the number of bytes in the instruction
in order to address the next instruction in sequence.
The instruction is then executed, and the same steps
are repeated using the new value of the instruction
address.
Branching
The normal sequential execution of instructions may
be changed by the use of the branching instructions
in order to perform subroutine linkage, decision
making, and loop control.
Subroutine linkage is provided by the BRANCH
AND LINK instructions, which permit not only the
introduction of a new instruction address but also
the preservation of the return address and associated
information.
Facilities for decision making are provided by the
BRANCH
struction inspects a two-bit condition code that re
flects the result of a majority of the arithmetic, logi
cal, and
can set the code in anyone of four states, and the
instruction BRANCH
any selection of these four states as the criterion for
branching. For example, the condition code reflects
such conditions as nonzero, first operand high,
equal, overflow, channel busy, and zero.
the condition code remains unchanged until modified
by an instruction that causes a different condition
code to be set.
The two bits of the condition code provide for
four possible condition code settings:
The specific meaning of any setting depends on the
operation that sets the condition code.
Loop control can be performed by the use of
BRANCH
address arithmetic and c0unting operations. For
some particularly frequent combinations of arithme
tic and tests, the instructions BRANCH
These branches, being specialized, provide increased
performance for these tasks.
Interruptions
The interruption system permits the CPU to change
state as a result of conditions external to the system,
in input/output
chine check, supervisor call, program, external,