placement provides for relative addressing of up to 4,095 bytes beyond the location designated by the
base address. In array-type calculations, the dis­
placement can be used to specify one of many items associated: with an element. In the processing of
records, the displacement can be used to identify
items within a record.
In forming the address, the base address and in­
dex are treated as unsigned 24-bit positive binary
integers. The displacement is similarly treated as a
12-bit positive binary integer, and 12 high-order
zeros are appended. The three are added as 24-bit
binary numbers, ignoring overflow. The sum is al­
ways 24 bits long. The bits of the generated address
are numbered 8-31, corresponding to the numbering
of the bas'e-address and index bits in the general
register.
A zero in any of the X2, Bl, or B2 fields indicates
the absenee of the corresponding address compo­
nent. For the absent component, a zero is used in
forming the address, regardless of the contents of
general register 0. A displacement of zero has no
special significance.
An instruction can designate the same general
register both for address computation and as the
location of an operand. Address computation is
completedl prior to the execution of the operation.
Unless otherwise indicated in the individual in­
struction definition, the computed operand address
designates an operand in main storage. When a
main-storage operand is designated, the address des­
ignates the leftmost byte of the operand. For
branching instructions, the second-operand address
is used as the branch address. For shifting instruc­
tions, the second-operand address is not used as an
address but specifies the shift amount. Prograr.n Status Word
The program status word (PSW) is 64 bits in length
and contains the information required for proper
program execution. The PSW includes the instruc­
tion address, condition code, and other fields. In
general, the PSW is used to control instruction se­
quencing and to hold and indicate the status of the
system in relation to the program currently being
executed. The active or controlling PSW is called the cun-ent PSW. By storing the current PSW during an
interruption, the status of the CPU can be preserved
for subsequent inspection. By loading a new PSW or
part of a PSW, the state of the CPU can be initial­
ized or changed.
22 System/370 Principles of Operation
Instruction Execution
In program execution, the instruction is fetched from
the location designated by the instruction address in
the current PSW. The instruction address is then
increased by the number of bytes in the instruction
in order to address the next instruction in sequence.
The instruction is then executed, and the same steps
are repeated using the new value of the instruction
address.
Branching
The normal sequential execution of instructions may
be changed by the use of the branching instructions
in order to perform subroutine linkage, decision­
making, and loop control.
Subroutine linkage is provided by the BRANCH
AND LINK instructions, which permit not only the
introduction of a new instruction address but also
the preservation of the return address and associated
information.
Facilities for decision making are provided by the
BRANCH ON CONDITION instruction. This in­
struction inspects a two-bit condition code that re­
flects the result of a majority of the arithmetic, logi­
cal, and I/O operations. Each of these operations
can set the code in anyone of four states, and the
instruction BRANCH ON CONDITION can specify
any selection of these four states as the criterion for
branching. For example, the condition code reflects
such conditions as nonzero, first operand high,
equal, overflow, channel busy, and zero. Once set,
the condition code remains unchanged until modified
by an instruction that causes a different condition
code to be set.
The two bits of the condition code provide for
four possible condition code settings: 0, 1, 2, and 3.
The specific meaning of any setting depends on the
operation that sets the condition code.
Loop control can be performed by the use of
BRANCH ON CONDITION to test the outcome of
address arithmetic and c0unting operations. For
some particularly frequent combinations of arithme­
tic and tests, the instructions BRANCH ON COUNT and BRANCH ON INDEX are provided.
These branches, being specialized, provide increased
performance for these tasks.
Interruptions
The interruption system permits the CPU to change
state as a result of conditions external to the system,
in input/output (I/O) units, or in the CPU itself. Six classes of interruption conditions are possible: ma­
chine check, supervisor call, program, external, I/O, and restart.
Each class has two related PSW s, called "old" and "new," in permanently assigned real main­
storage locations. In all classes, an interruption in­
volves storing information identifying the cause of
the interruption, storing the current PSW in its "old" position, and making the PSW at the "new" position
the current PSW.
The old PSW holds all necessary status informa­
tion of the CPU existing at the time of the interrup­
tion. If, at the conclusion of the program invoked by
the interruption, there is an instruction to make the
old PSW the current PSW, the CPU is restored to
the state prior to the interruption, and the interrupt­
ed program continues.
Sequence of Storage References
Conceptually, the CPU processes instructions one at
a time, with the execution of one instruction preced­
ing the execution of the following instruction, and
the execution of the instruction specified by a suc­
cessful branch follows the execution of the branch.
Similarly, an interruption takes place between execu­
tions of instructions.
The sequence of events implied by the processing
just described is sometimes called the conceptual
sequence or conceptual order.
Even though physical storage width and overlap
of instruction execution with storage accessing may
cause actual processing to be different, as observed
by a CPU itself, each operation is performed se­
quentially, with one instruction being fetched after
the preceding operation is completed and before the
execution of the current operation is begun. With
certain exceptions discussed in the section
"Interlocks Between Logical and Real Storage Refer­
ences" in the chapter "Dynamic Address Transla­
tion, " the results generated are those that would
have been obtained had the operation been per­
formed in the conceptual sequence. Thus, it is possi­
ble to modify an instruction in storage by the imme­
diately preceding instruction.
In very simple machines in which operations are
not overlapped, the conceptual and actual order are
essentially the same. However, in more complex
machines, overlapped operation, buffering of oper -
ands and results, and execution times which are
comparable to the propagation delays between units
can cause the actual order to differ considerably
from the conceptual order. In these machines, spe­
cial circuitry is employed to detect dependencies
between operations and ensure that the results ob­
tained are those that would have been obtained if
the operations had been performed in the conceptual
order. However, as observed by channels and other
CPUs, the sequence may appear to differ from the
conceptual order.
When only a single CPU is involved, it can nor­
mally be assumed that the execution of each instruc­
tion occurs as an indivisible event. However, in actu­
al operation, the execution of an instruction may
consist of a series of discrete steps. Depending on
the instruction, operands may be fetched and stored
in a piecemeal fashion, and some delay may occur
between fetching and storing a result. As a conse­
quence, another CPU or a channel may be able to
observe intermediate, or partially completed, results.
When the program on one CPU interacts with a
program on a channel or another CPU, the programs
may have to take into consideration that a single
operation may consist of a series of storage refer­
ences, that a storage reference may in turn consist of
a series of accesses, and that the conceptual and
actual sequences of these accesses may differ. Stor­
age references associated with instruction execution
are of the following types: instruction fetches, DAT
table fetches, storage operand references, and key­
in-storage accesses.
Instruction Fetch
Instruction fetching consists in fetching the one, two,
or three half words specified by the instruction ad­
dress in the current PSW. The immediate field of an
instruction is accessed as part of an instruction fetch.
If, however, an instruction specifies a storage ope­
rand at the location occupied by the instruction it­
self, the location is accessed both as an instruction
and as a storage operand. The fetch of the subject
instruction of EXECUTE is considered to be an
instruction fetch.
The bytes of an instruction may be fetched piece­
meal and are not necessarily accessed in a left-to­
right direction. The instruction may be fetched mul­
tiple times for a single execution; for example, it may
be fetched for testing the availability of dynamic­
address-translation tables or for inspection for
program-event exceptions, and it may be ref etched
for actual execution.
Instructions are not necessarily fetched in the
order in which they are conceptually executed and
are not necessarily fetched for each time they are
executed. In particular, the fetching of an instruction
may precede the storage-operand references for an
instruction that is conceptually earlier. The instruc­
tion fetch occurs prior to all storage-operand refer­
ences for all instructions that are conceptually later.
There is no limit established as to the number of
instructions which may be prefetched, and multiple
copies may be fetched of the contents of a single
storage location. As a result, the instruction executed Program Execution 23
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