is not necessarily the most recently fetched copy.
Storing caused by channels or by other CPUs does
not necessarily change the copy of prefetched in­
structions. However, if a store that is conceptually
earlier occurs on the same CPU using the same logi­
cal address as that by which the instruction is
fetched, the updated information is obtained.
All copies of prefetched instructions are discarded
when the CPU enters or leaves translation mode, when the DA T parameters are changed in control
registers 0 and 1 at a time when translation mode is
specified, by a serializing operation, and as the CPU enters the operating state. PTogranumrnng As observed by a CPU itself, instruction prefetching
is not normally apparent; the only exception occurs
when than one logical page address is translat­
ed to a single real page address. This is described in
the section "Interlocks Between Logical and Real
Storage Re:ferences" in the chapter "Dynamic Ad­
dress Translation." The following are some effects of instruction pre- I fetching on the execution of a program as viewed by
another Cl>U. If a program in one CPU changes the contents of
a storage location and then sets a flag to indicate
that the change has been made, a program in anoth­
er CPU can test and find the flag set but subse·· quently can branch to the modified locations and
execute tht,ir original contents. Additionally, when a
channel or another CPU modifies an instruction, it is
possible for a CPU to recognize the changes to some
but not all bit positions of the instruction.
It is possible for a CPU to prefetch an instruction
and subsequently, before the instruction is executed,
for another CPU to change the key in storage. As a
result, a CPU may appear to execute instructions
from a storage location that is protected.
DAT TalJle Fetches
Fetching of dynamic address translation (DAT) ta­
ble entries may occur as foHows: 1. DAT entries may be prefetched into the
trans!lation-Iookaside buffer (TLB) and used
from the TLB without ref etching from storage,
until a PURGE TLB (PTLB) instruction is
executed. DAT entries may be fetched at any
time they are attached and valid, including dur­
ing the execution of conceptually previous in­
structions, and are not necessarily fetched in
the order conceptually called for.
2. A DAT table entry may be fetched piecemeal,
a byte at a time, from main storage. However,
no operand stores by this CPU or any other
24 System/370 Principles of Operation CPU are permitted, to the same location, be­
tween the fetches of the bytes.
3. A DAT table entry may be fetched even after
some operand references for the instruction
have already occurred. The fetch may occur as
late as just prior to the actual byte access re­
quiring the DAT entry.
4. A DAT table entry may be fetched for each use
of the address, including pretesting, if per­
formed, and for each reference to each byte of
each operand.
5. The DAT page-table-entry fetch precedes the
reference to the page. When a page-table en­
try goeS from inactive to active status, the
fetch of the associated segment-table entry
precedes the fetch of the page-table entry.
For translation of the second operand of LOAD REAL ADDRESS, the segment-table-entry fetch
precedes the page-table-entry fetch. The entries are
fetched using the same rule as (2) above. The rela­
tionship of these two fetches to other references
follows the rules for storage-operand fetches.
Key-in-Storage Accesses
References to the key in storage are handled as fol­
lows:
1. Whenever a reference to main storage is made
and protection applies to the reference, the five
access control bits associated with the storage
location are inspected concurrently with the
reference to the storage location.
2. When storing is performed, the change bit is set
in the associated key in storage concurrently
with the store operation.
3. The instruction SET STORAGE KEY causes
the five access control bits and the change bit
to be set concurrently in the key in storage.
The access to the key in storage for SET STORAGE KEY follows the sequence rules
for storage-operand store references, and is a
single-access reference.
4. The instruction INSERT STORAGE KEY
provides a consistent image of the field consist­
ing of the five access control bits and the
change bit. The access to the key in storage for
INSERT STORAGE KEY follows the se­
quence rules for storage-operand fetch refer­
ences, and is a single-access reference.
5. The instruction RESET REFERENCE BIT
modifies only the reference bit. All other bits
of the key in storage remain unchanged. The
access to the key in storage for RESET REF­
ERENcE BIT follows the sequence rules for

storage-operand update references. The refer­
ence bit is the only bit which is updated.
The record of references provided by the refer­
ence bit is not necessarily accurate, and the handling
of the reference bit is not subject to the concurrency
rules. However, in the majority of situations, refer­
ence recording approximately coincides with the
storage reference.
Storage-Operand References
A storage-operand reference is the fetching or stor­
ing of the explicit operand or operands in the main­
storage locations specified by the instruction.
During the execution of an instruction, all, or a
portion, of the storage operands for that instruction
may be fetched, intermediate results may be main­
tained for subsequent modification, and final results
may be temporarily held prior to placing them in
main storage. Stores caused by channels or by other CPUs do not necessarily affect these intermediate
results. Storage-operand references are of three
types: fetches, stores, and updates. Storage-Operand Fetch References
When the bytes of a storage operand participate in
the instruction execution only as a source, the refer­
ence to the location is called a storage-operand fetch
reference. A fetch reference is identified in the indi­
vidual instruction definition by indicating that the
access exception is for fetch.
All bits within a single byte of a fetch reference
are accessed concurrently. When an operand consists
of more than one byte, the bytes may be fetched
piecemeal a byte at a time from main storage. Unless
otherwise specified, the bytes are not necessarily
fetched in any particular order. The fetch reference
for the operands of some instructions is specified to
be concurrent Within a block. In this case, no stores
by any other 'CPU ,are permitted, to the same loca­
tion, between the fetches of the bytes within a block.
Storage-Operand Store References
When the bytes of a storage operand participate in
the instruction execution only to the extent of being
replaced by the result, the reference to the location
is called a storage-operand store reference. A store
reference is identified in the individual instruction definition by indicating that the access exception is
for store.
All bits within a single byte of a store reference
are accessed concurrently. When an operand consists
of more than one byte, the bytes may be stored
piecemeal a byte at a time into main storage. Unless
otherwise specified, the bytes are not necessarily
stored in any particular order. The store reference
for some instructions is specified to be concurrent
within a block. In this case, no stores or fetches by
any other CPU are permitted, to the same location,
between the stores of bytes within a block.
A CPU may delay storing results into main stor­
age. There is no defined limit on the length of time
that results may remain pending before they are
stored.
This delay does not affect the order in which re­
sults are placed in main storage. The results of one
instruction are placed in main storage after the re­
sults of all preceding instructions have been placed
in main storage and before any results of the suc­
ceeding instructions are stored. The results of any
one instruction are stored in the order specified for
that instruction.
A CPU does not fetch operands, or dynamic­
address-translation table entries, from a main­
storage location until all information destined for
that real main-storage location by that CPU has
been placed in main storage. Prefetched instructions
may appear to be updated prior to the information
appearing in storage.
The stores are necessarily completed only as a
result of a serializing operation and before the CPU enters the stopped state.
Storage-Operand Update References
In some instructions, the storage-operand location
participates both as a source and as a destination. In
these cases, the reference to the location consists
first of a fetch and subsequently of a store. The com­
bination of the two accesses is referred to as an up­
date reference. Instnictions such as MOVE ZONES, TRANSLATE, OR (OI), and ADD DECIMAL
cause an update to the first-operand location. In
most cases, no special interlock is provided between
the fetch and store, and accesses by channels and
other CPUs are permitted. An update reference is
identified in the individual instruction definition by
indicating that the access exception is for both fetch
and store. The fetch and store accesses associated
with an update reference are not necessarily made
contiguously, and it is possible for another CPU or
channel to make one or more interleaved accesses to
the same location. The interleaved accesses can be
either fetches or stores and can be associated with
either an update or an interlocked-update reference.
Three instructions perform an update which is
interlocked against accesses to the same location
during the execution of the instruction. The instruc­
tion TEST AND SET (TS) causes an interlocked
update, and the instructions COMPARE AND SW AP (CS) and COMPARE DOUBLE AND
Program Execution 25