Each class has two related PSW s, called "old" and "new," in permanently assigned real main­
storage locations. In all classes, an interruption in­
volves storing information identifying the cause of
the interruption, storing the current PSW in its "old" position, and making the PSW at the "new" position
the current PSW.
The old PSW holds all necessary status informa­
tion of the CPU existing at the time of the interrup­
tion. If, at the conclusion of the program invoked by
the interruption, there is an instruction to make the
old PSW the current PSW, the CPU is restored to
the state prior to the interruption, and the interrupt­
ed program continues.
Sequence of Storage References
Conceptually, the CPU processes instructions one at
a time, with the execution of one instruction preced­
ing the execution of the following instruction, and
the execution of the instruction specified by a suc­
cessful branch follows the execution of the branch.
Similarly, an interruption takes place between execu­
tions of instructions.
The sequence of events implied by the processing
just described is sometimes called the conceptual
sequence or conceptual order.
Even though physical storage width and overlap
of instruction execution with storage accessing may
cause actual processing to be different, as observed
by a CPU itself, each operation is performed se­
quentially, with one instruction being fetched after
the preceding operation is completed and before the
execution of the current operation is begun. With
certain exceptions discussed in the section
"Interlocks Between Logical and Real Storage Refer­
ences" in the chapter "Dynamic Address Transla­
tion, " the results generated are those that would
have been obtained had the operation been per­
formed in the conceptual sequence. Thus, it is possi­
ble to modify an instruction in storage by the imme­
diately preceding instruction.
In very simple machines in which operations are
not overlapped, the conceptual and actual order are
essentially the same. However, in more complex
machines, overlapped operation, buffering of oper -
ands and results, and execution times which are
comparable to the propagation delays between units
can cause the actual order to differ considerably
from the conceptual order. In these machines, spe­
cial circuitry is employed to detect dependencies
between operations and ensure that the results ob­
tained are those that would have been obtained if
the operations had been performed in the conceptual
order. However, as observed by channels and other
CPUs, the sequence may appear to differ from the
conceptual order.
When only a single CPU is involved, it can nor­
mally be assumed that the execution of each instruc­
tion occurs as an indivisible event. However, in actu­
al operation, the execution of an instruction may
consist of a series of discrete steps. Depending on
the instruction, operands may be fetched and stored
in a piecemeal fashion, and some delay may occur
between fetching and storing a result. As a conse­
quence, another CPU or a channel may be able to
observe intermediate, or partially completed, results.
When the program on one CPU interacts with a
program on a channel or another CPU, the programs
may have to take into consideration that a single
operation may consist of a series of storage refer­
ences, that a storage reference may in turn consist of
a series of accesses, and that the conceptual and
actual sequences of these accesses may differ. Stor­
age references associated with instruction execution
are of the following types: instruction fetches, DAT
table fetches, storage operand references, and key­
in-storage accesses.
Instruction Fetch
Instruction fetching consists in fetching the one, two,
or three half words specified by the instruction ad­
dress in the current PSW. The immediate field of an
instruction is accessed as part of an instruction fetch.
If, however, an instruction specifies a storage ope­
rand at the location occupied by the instruction it­
self, the location is accessed both as an instruction
and as a storage operand. The fetch of the subject
instruction of EXECUTE is considered to be an
instruction fetch.
The bytes of an instruction may be fetched piece­
meal and are not necessarily accessed in a left-to­
right direction. The instruction may be fetched mul­
tiple times for a single execution; for example, it may
be fetched for testing the availability of dynamic­
address-translation tables or for inspection for
program-event exceptions, and it may be ref etched
for actual execution.
Instructions are not necessarily fetched in the
order in which they are conceptually executed and
are not necessarily fetched for each time they are
executed. In particular, the fetching of an instruction
may precede the storage-operand references for an
instruction that is conceptually earlier. The instruc­
tion fetch occurs prior to all storage-operand refer­
ences for all instructions that are conceptually later.
There is no limit established as to the number of
instructions which may be prefetched, and multiple
copies may be fetched of the contents of a single
storage location. As a result, the instruction executed Program Execution 23

is not necessarily the most recently fetched copy.
Storing caused by channels or by other CPUs does
not necessarily change the copy of prefetched in­
structions. However, if a store that is conceptually
earlier occurs on the same CPU using the same logi­
cal address as that by which the instruction is
fetched, the updated information is obtained.
All copies of prefetched instructions are discarded
when the CPU enters or leaves translation mode, when the DA T parameters are changed in control
registers 0 and 1 at a time when translation mode is
specified, by a serializing operation, and as the CPU enters the operating state. PTogranumrnng As observed by a CPU itself, instruction prefetching
is not normally apparent; the only exception occurs
when than one logical page address is translat­
ed to a single real page address. This is described in
the section "Interlocks Between Logical and Real
Storage Re:ferences" in the chapter "Dynamic Ad­
dress Translation." The following are some effects of instruction pre- I fetching on the execution of a program as viewed by
another Cl>U. If a program in one CPU changes the contents of
a storage location and then sets a flag to indicate
that the change has been made, a program in anoth­
er CPU can test and find the flag set but subse·· quently can branch to the modified locations and
execute tht,ir original contents. Additionally, when a
channel or another CPU modifies an instruction, it is
possible for a CPU to recognize the changes to some
but not all bit positions of the instruction.
It is possible for a CPU to prefetch an instruction
and subsequently, before the instruction is executed,
for another CPU to change the key in storage. As a
result, a CPU may appear to execute instructions
from a storage location that is protected.
DAT TalJle Fetches
Fetching of dynamic address translation (DAT) ta­
ble entries may occur as foHows: 1. DAT entries may be prefetched into the
trans!lation-Iookaside buffer (TLB) and used
from the TLB without ref etching from storage,
until a PURGE TLB (PTLB) instruction is
executed. DAT entries may be fetched at any
time they are attached and valid, including dur­
ing the execution of conceptually previous in­
structions, and are not necessarily fetched in
the order conceptually called for.
2. A DAT table entry may be fetched piecemeal,
a byte at a time, from main storage. However,
no operand stores by this CPU or any other
24 System/370 Principles of Operation CPU are permitted, to the same location, be­
tween the fetches of the bytes.
3. A DAT table entry may be fetched even after
some operand references for the instruction
have already occurred. The fetch may occur as
late as just prior to the actual byte access re­
quiring the DAT entry.
4. A DAT table entry may be fetched for each use
of the address, including pretesting, if per­
formed, and for each reference to each byte of
each operand.
5. The DAT page-table-entry fetch precedes the
reference to the page. When a page-table en­
try goeS from inactive to active status, the
fetch of the associated segment-table entry
precedes the fetch of the page-table entry.
For translation of the second operand of LOAD REAL ADDRESS, the segment-table-entry fetch
precedes the page-table-entry fetch. The entries are
fetched using the same rule as (2) above. The rela­
tionship of these two fetches to other references
follows the rules for storage-operand fetches.
Key-in-Storage Accesses
References to the key in storage are handled as fol­
lows:
1. Whenever a reference to main storage is made
and protection applies to the reference, the five
access control bits associated with the storage
location are inspected concurrently with the
reference to the storage location.
2. When storing is performed, the change bit is set
in the associated key in storage concurrently
with the store operation.
3. The instruction SET STORAGE KEY causes
the five access control bits and the change bit
to be set concurrently in the key in storage.
The access to the key in storage for SET STORAGE KEY follows the sequence rules
for storage-operand store references, and is a
single-access reference.
4. The instruction INSERT STORAGE KEY
provides a consistent image of the field consist­
ing of the five access control bits and the
change bit. The access to the key in storage for
INSERT STORAGE KEY follows the se­
quence rules for storage-operand fetch refer­
ences, and is a single-access reference.
5. The instruction RESET REFERENCE BIT
modifies only the reference bit. All other bits
of the key in storage remain unchanged. The
access to the key in storage for RESET REF­
ERENcE BIT follows the sequence rules for