When an instruction has two storage the first of which causes an update reference and the
second a fetch reference, it is unpredictable which
operand is fetched first, or how much of one oper­
and is fetched before the other operand is fetched.
Similarly, it is unpredictable how much of the result
is processed before it is returned to storage. In the
case of destructively overlapping operands, the por­
tion of the second operand which is common to the
first is not necessarily fetched from storage.
Programming Notes
The independent fetching of a single location for
each of two operands may affect the program execu­
tion in the following situation.
When the same main-storage location is designat­
ed by two operand addresses of an instruction, and a
channel or another CPU causes the contents of the
location to change during execution of the instruc­
tion, the old and new values of the location may be
used simultaneously. For example, comparison of a
field to itself may yield a result other than equal, or EXCLUSIVE-ORing of a field to itself may yield a
result other than zero.
Serialization
All interruptions, and the execution of certain in­
structions, cause serialization of CPU operation.
Execution of a serialization function consists in com­
pleting aU conceptually prior storage accesses by this CPU, as observed by channels and other CPUs, before the conceptually following storage accesses I occur. Sedalization affect.s the order of all accesses
by this CPU to storage and to the key in storage,
except for those associated with DAT -table-entry
fetch.
Serialization is performed by all interruptions and
by the execution of the following instructions:
1. These general instructions: BRANCH ON CONDITION (BCR) with the Rl and R2 fields
containing all ones and all zeros, respectively,
and COMPARE AND SWAP, COMPARE DOUBLE AND SWAP, STORE CLOCK, SUPERVISOR CALL, and TEST AND SET.
2. LOADPSW. 3. PURGE TLB and SET PREFIX, which also
cause the translation-look aside buffer to be
purged.
4. All I/O instructions.
5. The signaling instructions: READ DIRECT,
WR1[TE DIRECT, and SIGNAL PROC­ ESSOR. The sequence of events associated with a serializ-
28 System/370 Principles of Operation ing operation is as follows: • All conceptually previous CPU storage accesses
by this CPU are completed, as observed by
channels and other CPUs. This includes all
conceptually previous stores and changes to
keys in storage. • The normal function associated with the serial­
izing operation is performed. In the case of
instruction execution, operands are fetched,
and the storing of results is completed. The
exceptions are LPSW and SPX, in which the
operands may be fetched before previous
stores have been completed, and interruptions,
in which the interruption code and associated
fields may be stored prior to the serialization.
The fetching of the serializing instruction oc­
curs before the execution of the instruction and
may precede the execution of previous instruc­
tions, but may not precede the completion of
the previous serializing operation. In the case
of an interruption, the old PSW, the interrup­
tion code, and other information, if any, are
stored, and the new PSW is fetched. • Finally, instruction fetch and operand accesses
for conceptually subsequent operations may
continue.
A serializing function affects the order of storage
accesses that are under the control of the CPU in
which the serializing function takes place. It does
not affect the order of storage accesses caused by a
program in a channel or another CPU. Programming Notes
The following are some effects of a serializing opera­
tion:
1. When an instruction changes the contents of a
storage lo-cation that is used as a source of a
following instruction and when different ad­
dresses are used to designate the location for
storing the result and fetching the instruction, a
serializing operation following the change en­
sures that the modified instruction is executed.
2. When a serializing operation takes place, chan­
nels and any other CPU observe instruction
and operand fetching and result storing to take
place in the order established by the serializing
operation.
Storing into a location from which a serializing
instruction is fetched-does not necessarily affect the
execution of the serializing instruction unless a seri­
alizing function has been performed after the storing
and before the execution of the serializing instruc­
tion.

System Control Contents CPU States Wait and Running States Problem and Supervisor States. Stopped and Operating States. Control Modes BC Mode. EC Mode. Set-System-Mask Suppression Program Status Word Program Status Word Format in BC Mode Program Status Word Format in EC Mode
Exceptions Associated with the PSW .
Early Exception Recognition
Late Exception Recognition Control Registers
Key in Storage . Protection Protection Action
Accesses Protected Monitoring Program-Event Recording Control Register Allocation Operation Identification of Cause Priority of Indication Storage Area Designation
Program Events . Successful Branching I nstruction Fetching Storage Alteration .
General-Register Alteration I ndication of Events Concurrently with Other I nterruption Conditions
Direct Control .30
.30
.30
.30
.31
.32
.32
.32
.32
.33
.34
.35
.35
.35
.36
.38
.38
.38
.39
.39
.39
.40
.40
.41
.41
.42
.42
.42
.42
.42
.43
.43
.46
.46
.46
.46
.47
.47
T ime-of-Day Clock Format States Setting and I nspection of Value Clock Comparator CPU Timer Interval Timer Externally Initiated Functions
Resets CPU Reset Initial CPU Reset 1/0 System Reset Program Reset Initial Program Reset System-Clear Reset Power-On Reset . Store Status . I nitial Loading
This chapter provides the detailed description of a
number of facilities that provide for switching the
status of the system, for protecting a program from
interference by another program, for initiating cer­
tain operations externally, and, in general, for en­
hancing the efficiency, utility, and programmability
of the system. ·48 .49
.50
.50
. 51
.51
.51
. 51
.52
.53
.53
.54
.54
The information determining the state and opera­
tion of the CPU resides in the program status word
(PSW) and in control registers. Additional status and
control information appears in low-order locations
of main storage. By providing a supervisor state and
a set of instructions that are valid only in the super­
visor state for changing the contents of the PSW and
System Control 29