control registers, a means is provided for avoiding
unauthorized or inadvertent change to the system
state.
The protection facility permits the protection of
the contents of main storage from destruction or
misuse caused by erroneous or unauthorized storing
or fetching by a program.
Four timing facilities are provided for measuring
time: the time-of -day clock permits indication of
calendar time with a resolution of 1 microsecond and
a period in excess of one hundred years; the clock
comparator permits a program to be alerted at a
particular instant of real time; and the CPU timer
and interval timer provide a means for a program to
be alerted after a specified time interval has elapsed.
Additionally, the following three facilities are
provided: monitoring, program-event recording, and
direct control. The monitoring facility is useful for
performing various measurement functions, whereas
program-event recording provides a means to assist
in debugging programs.
A set of externally initiated functions is provided
for initializing the system or for inspecting its state.
These functions include reset, store status, and initial
program loading. CPU States Excluding facilities that are provided for thc mainte­
nance of equipment, three types of state alternatives
in the CPU are distinguished: wait-running,
problem·-supervisor, and stopped-operating. These
states differ in the way they affect CPU functions
and in the way their status is indicated and switched.
Wait Q'nd Running States
In the wait state no instructions are processed,
whereas in the running state instruction fetching and
execution proceed in the normal manner. The CPU is interruptible in the wait state, provided it is ena­
bled for the interruption source.
The CPU is in the wait state when bit 14 of the PSW is one. When bit 14 is zero, the CPU is in the
running state.
The wait state is indicated in the operator section
of the system console by the wait light. No explicit
operator control is provided for changing the state.
The updating of timing facilities is not affected by
whether the CPU is in the wait or running state. ProbleJ'II and Supervisor States
The alternative between problem and supervisor
state determines whether the full set of instructions
is valid.
In the supervisor state all instructions are valid. In 30 System/370 Principles of Operation
the problem state only those instructions are valid
that cannot be used to affect system integrity and
that do not pertain to maintenance or model­
dependent functions. The instructions that are not
valid in the problem state are called privileged in­
structions; they include those which modify or in­
spect keys in storage, those which modify or inspect
the system control fields in the PSW and in control
registers, and those which pertain to timing facilities,
prefixing, inter-CPU communication, and
input/ output. A privileged instruction encountered
in the problem state constitutes a privileged-­
operation exception and causes a program interrup­
tion.
The CPU is in the problem state when bit 15 of
the PSW is one. When bit 15 is zero, the CPU is in
the supervisor state.
The updating of timing facilities is not affected by
whether the CPU is in the problem or supervisor
state.
Programming Notes
The CPU may be switched between wait-running
and problem-supervisor states only by introducing
an entire new PSW. This may be performed by LOAD PSW, an interruption (including a supervisor­
call interruption), or initial program loading.
The instruction LOAD PSW can be used to
switch from the supervisor to the problem state and
from the running to the wait state but not vice versa.
To allow return from an interruption-handling rou­
tine by LOAD PSW, the PSW for the interruption­
handling routine must specify the supervisor state.
In the wait state the CPU does not make repeated
references to main storage; therefore, wait state is
suitable for delaying operation until an interruption
occurs. References, however, may be made due to I/O operations and for updating the interval timer.
To leave wait state without manual intervention, the CPU must be enabled for the interruption source.
Stopped and Operating States
When the CPU is in the stopped state, instructions
and interruptions, other than the restart interruption,
are not executed. In the operating state, the CPU executes instructions and interruptions, subject to
the control of the wait bit and mask bits and in the
manner specified by the setting of the rate control
on the system console.
A change between the stopped and operating
states can be effected by manual intervention or by
use of the SIGNAL PROCESSOR instruction. The
stopped state is not controlled or identified by a bit
in the PSW.

The state of the CPU is changed from stopped to
operating by the following events: • When the start key on the system console is
activated or when the CPU accepts the start
order specified by a SIGNAL PROCESSOR instruction addressing this CPU. However, the
effect of start is unpredictable when the stop­
ped state has been entered by means of a reset. • When a restart interruption occurs, either as a
result of the activation of the restart key or the
execution of the SIGNAL PROCESSOR re­
start order. • When initial program loading is successfully
completed.
The state of the CPU is changed from operating
to stopped by the performance of the stop function.
The execution of the stop function is initiated: • When the stop key on the system console is
activated while the CPU is in the operating
state. • When the CPU accepts a stop or stop-and­
store-status order specified by a SIGNAL PROCESSOR instruction addressing this CPU while the CPU is in the operating state. • When the CPU has finished the execution of an
instruction with the rate control set to instruc­
tion step.
When the stop function is performed, the tran­
sition from the operating to the stopped state occurs
at the end of the current unit of operation. When the CPU is in the wait state, the transition takes place
immediately provided no interruptions are pending
for which the CPU is enabled. In the case of the
interruptible instructions, the amount of data pro­
cessed in a unit of operation depends on the particu­
lar instruction and may depend on the model.
All interruptions pending and not disallowed are
taken while the CPU is still in the operating state.
They cause the old PSW to be stored and the new PSW to be fetched before the stopped state is en­
tered. When the CPU is in the stopped state, inter­
ruption conditions may be ignored or remain pend­
ing, the action being the same as when the CPU is
disabled for the conditions.
The CPU is placed in the stopped state also: • After the completion of CPU reset, except
when the reset operation is performed as part
of initial program loading, and • When an address comparison indicates equality
and stopping on the matc1;l is specified.
The execution of CPU reset is described in "Resets" in this chapter, and the stopping due to
address comparison is described in "Address-
Compare Controls" in the chapter" System Con­ sole." Additionally, the CPU may, depending on the
model, temporarily enter the stopped state when the
restart interruption is initiated with the CPU in the
operating state.
When the CPU is in the stopped state, the manual
indicator on the system console is on.
Two other alternatives to the stopped and operat­
ing states exist: the load state and the check-stop
state. The CPU is in the load state during the initial­
program-loading operation. The check-stop state is
entered on certain types of machine malfunctioning
and is described in the chapter "Machine-Check
Handling. " A CPU may have other alternatives to the stop­
ped and operating states for maintenance and diag­
nostic functions and for the purpose of displaying
and entering information via the console.
The interval timer is updated only when the CPU is in the operating state. The CPU timer is updated
when the CPU is in the operating state or the load
state.
Programming Notes
Except for the relationship between execution
time and real time, the execution of a program is not
affected by stopping the CPU. When, because of a machine malfunction, the CPU is unable to end the execution of an instruc­
tion, the stop function is ineffective, and a reset
function has to be invoked instead. A similar situa­
tion occurs in the case of an unending interruption
sequence resulting from a PSW with a format error
or from a direct interruption condition, such as one
due to the CPU timer.
Input/ output operations continue to completion
after the CPU enters the stopped state. The inter­
ruption conditions due to completion of I/O opera­
tions remain pending when the CPU is in the stop­
ped state.
Control Modes
Two modes are provided for the formatting and use
of control and status information: basic-control
(BC) mode and extended-control (EC) mode. The
mode is specified by the contents of bit position 12
of the program status word (PSW). The two modes determine the allocation of bit
positions within the PSW, the use of permanently
assigned locations in main storage for storing the
interruption code and the instruction-length code on
some classes of interruptions, the controlling of I/O interruptions for channels 0-5, and the handling of
reference and change bits by INSERT STORAGE System Control 31