The state of the CPU is changed from stopped to
operating by the following events:• When the start key on the system console is
activated or when theCPU accepts the start
order specified by a SIGNALPROCESSOR instruction addressing this CPU. However, the
effect of start is unpredictable when the stop
ped state has been entered by means of a reset.• When a restart interruption occurs, either as a
result of the activation of the restart key or the
execution of the SIGNALPROCESSOR re
start order.• When initial program loading is successfully
completed.
The state of theCPU is changed from operating
to stopped by the performance of the stop function.
The execution of the stop function is initiated:• When the stop key on the system console is
activated while theCPU is in the operating
state.• When the CPU accepts a stop or stop-and
store-status order specified by a SIGNALPROCESSOR instruction addressing this CPU while the CPU is in the operating state. • When the CPU has finished the execution of an
instruction with the rate control set to instruc
tion step.
When the stop function is performed, the tran
sition from the operating to the stopped state occurs
at the end of the current unit of operation. When theCPU is in the wait state, the transition takes place
immediately provided no interruptions are pending
for which theCPU is enabled. In the case of the
interruptible instructions, the amount of data pro
cessed in a unit of operation depends on the particu
lar instruction and may depend on the model.
All interruptions pending and not disallowed are
taken while theCPU is still in the operating state.
They cause the oldPSW to be stored and the new PSW to be fetched before the stopped state is en
tered. When theCPU is in the stopped state, inter
ruption conditions may be ignored or remain pend
ing, the action being the same as when theCPU is
disabled for the conditions.
TheCPU is placed in the stopped state also: • After the completion of CPU reset, except
when the reset operation is performed as part
of initial program loading, and• When an address comparison indicates equality
and stopping on thematc1;l is specified.
The execution ofCPU reset is described in "Resets" in this chapter, and the stopping due to
address comparison is described in "Address-
Compare Controls" in the chapter" System Console." Additionally, the CPU may, depending on the
model, temporarily enter the stopped state when the
restart interruption is initiated with theCPU in the
operating state.
When theCPU is in the stopped state, the manual
indicator on the system console is on.
Two other alternatives to the stopped and operat
ing states exist: the load state and the check-stop
state. TheCPU is in the load state during the initial
program-loading operation. The check-stop state is
entered on certain types of machine malfunctioning
and is described in the chapter "Machine-Check
Handling." A CPU may have other alternatives to the stop
ped and operating states for maintenance and diag
nostic functions and for the purpose of displaying
and entering information via the console.
The interval timer is updated only when theCPU is in the operating state. The CPU timer is updated
when theCPU is in the operating state or the load
state.
Programming Notes
Except for the relationship between execution
time and real time, the execution of a program is not
affected by stopping theCPU. When, because of a machine malfunction, the CPU is unable to end the execution of an instruc
tion, the stop function is ineffective, and a reset
function has to be invoked instead. A similar situa
tion occurs in the case of an unending interruption
sequence resulting from aPSW with a format error
or from a direct interruption condition, such as one
due to theCPU timer.
Input/ output operations continue to completion
after theCPU enters the stopped state. The inter
ruption conditions due to completion ofI/O opera
tions remain pending when theCPU is in the stop
ped state.
Control Modes
Two modes are provided for the formatting and use
of control and status information: basic-control
(BC) mode and extended-control (EC) mode. The
mode is specified by the contents of bit position 12
of the program status word(PSW). The two modes determine the allocation of bit
positions within thePSW, the use of permanently
assigned locations in main storage for storing the
interruption code and the instruction-length code on
some classes of interruptions, the controlling ofI/O interruptions for channels 0-5, and the handling of
reference and change bits by INSERTSTORAGE System Control 31
operating by the following events:
activated or when the
order specified by a SIGNAL
effect of start is unpredictable when the stop
ped state has been entered by means of a reset.
result of the activation of the restart key or the
execution of the SIGNAL
start order.
completed.
The state of the
to stopped by the performance of the stop function.
The execution of the stop function is initiated:
activated while the
state.
store-status order specified by a SIGNAL
instruction with the rate control set to instruc
tion step.
When the stop function is performed, the tran
sition from the operating to the stopped state occurs
at the end of the current unit of operation. When the
immediately provided no interruptions are pending
for which the
interruptible instructions, the amount of data pro
cessed in a unit of operation depends on the particu
lar instruction and may depend on the model.
All interruptions pending and not disallowed are
taken while the
They cause the old
tered. When the
ruption conditions may be ignored or remain pend
ing, the action being the same as when the
disabled for the conditions.
The
when the reset operation is performed as part
of initial program loading, and
and stopping on the
The execution of
address comparison is described in "Address-
Compare Controls" in the chapter" System Con
model, temporarily enter the stopped state when the
restart interruption is initiated with the
operating state.
When the
indicator on the system console is on.
Two other alternatives to the stopped and operat
ing states exist: the load state and the check-stop
state. The
program-loading operation. The check-stop state is
entered on certain types of machine malfunctioning
and is described in the chapter "Machine-Check
Handling.
ped and operating states for maintenance and diag
nostic functions and for the purpose of displaying
and entering information via the console.
The interval timer is updated only when the
when the
state.
Programming Notes
Except for the relationship between execution
time and real time, the execution of a program is not
affected by stopping the
tion, the stop function is ineffective, and a reset
function has to be invoked instead. A similar situa
tion occurs in the case of an unending interruption
sequence resulting from a
or from a direct interruption condition, such as one
due to the
Input/ output operations continue to completion
after the
ruption conditions due to completion of
tions remain pending when the
ped state.
Control Modes
Two modes are provided for the formatting and use
of control and status information: basic-control
(BC) mode and extended-control (EC) mode. The
mode is specified by the contents of bit position 12
of the program status word
positions within the
assigned locations in main storage for storing the
interruption code and the instruction-length code on
some classes of interruptions, the controlling of
reference and change bits by INSERT