The state of the CPU is changed from stopped to
operating by the following events: When the start key on the system console is
activated or when the CPU accepts the start
order specified by a SIGNAL PROCESSOR instruction addressing this CPU. However, the
effect of start is unpredictable when the stop­
ped state has been entered by means of a reset. When a restart interruption occurs, either as a
result of the activation of the restart key or the
execution of the SIGNAL PROCESSOR re­
start order. When initial program loading is successfully
completed.
The state of the CPU is changed from operating
to stopped by the performance of the stop function.
The execution of the stop function is initiated: When the stop key on the system console is
activated while the CPU is in the operating
state. When the CPU accepts a stop or stop-and­
store-status order specified by a SIGNAL PROCESSOR instruction addressing this CPU while the CPU is in the operating state. When the CPU has finished the execution of an
instruction with the rate control set to instruc­
tion step.
When the stop function is performed, the tran­
sition from the operating to the stopped state occurs
at the end of the current unit of operation. When the CPU is in the wait state, the transition takes place
immediately provided no interruptions are pending
for which the CPU is enabled. In the case of the
interruptible instructions, the amount of data pro­
cessed in a unit of operation depends on the particu­
lar instruction and may depend on the model.
All interruptions pending and not disallowed are
taken while the CPU is still in the operating state.
They cause the old PSW to be stored and the new PSW to be fetched before the stopped state is en­
tered. When the CPU is in the stopped state, inter­
ruption conditions may be ignored or remain pend­
ing, the action being the same as when the CPU is
disabled for the conditions.
The CPU is placed in the stopped state also: After the completion of CPU reset, except
when the reset operation is performed as part
of initial program loading, and When an address comparison indicates equality
and stopping on the matc1;l is specified.
The execution of CPU reset is described in "Resets" in this chapter, and the stopping due to
address comparison is described in "Address-
Compare Controls" in the chapter" System Con­ sole." Additionally, the CPU may, depending on the
model, temporarily enter the stopped state when the
restart interruption is initiated with the CPU in the
operating state.
When the CPU is in the stopped state, the manual
indicator on the system console is on.
Two other alternatives to the stopped and operat­
ing states exist: the load state and the check-stop
state. The CPU is in the load state during the initial­
program-loading operation. The check-stop state is
entered on certain types of machine malfunctioning
and is described in the chapter "Machine-Check
Handling. " A CPU may have other alternatives to the stop­
ped and operating states for maintenance and diag­
nostic functions and for the purpose of displaying
and entering information via the console.
The interval timer is updated only when the CPU is in the operating state. The CPU timer is updated
when the CPU is in the operating state or the load
state.
Programming Notes
Except for the relationship between execution
time and real time, the execution of a program is not
affected by stopping the CPU. When, because of a machine malfunction, the CPU is unable to end the execution of an instruc­
tion, the stop function is ineffective, and a reset
function has to be invoked instead. A similar situa­
tion occurs in the case of an unending interruption
sequence resulting from a PSW with a format error
or from a direct interruption condition, such as one
due to the CPU timer.
Input/ output operations continue to completion
after the CPU enters the stopped state. The inter­
ruption conditions due to completion of I/O opera­
tions remain pending when the CPU is in the stop­
ped state.
Control Modes
Two modes are provided for the formatting and use
of control and status information: basic-control
(BC) mode and extended-control (EC) mode. The
mode is specified by the contents of bit position 12
of the program status word (PSW). The two modes determine the allocation of bit
positions within the PSW, the use of permanently
assigned locations in main storage for storing the
interruption code and the instruction-length code on
some classes of interruptions, the controlling of I/O interruptions for channels 0-5, and the handling of
reference and change bits by INSERT STORAGE System Control 31
KEY. Furthermore, program-event recording and
dynamic address translation can be specified only in
the EC mode, as the corresponding control bits in
the PSW are provided only in the EC mode.
BC Mode
In the BC mode, the PSW has the same format as in System/360, and, except for the old PSW stored on
a machine-check interruption, the interruption code
and the instruction-length code appear in the PSW. As in System/360, interruptions from channels 0-5 are subject to the control by PSW bits 0-5, and IN­
SERT STORAGE KEY provides zeros in bit posi­
tions 29 and 30 that correspond to the reference and
change bits. A number of additional permanently
assigned storage locations, however, are used during
interruptions associated with extended or new func­
tions, including those for storing the machine-check
interruption code and those for storing the monitor
code and monitor class number as the result of a
monitor-call event.
The BC mode is specified when PSW bit 12 is O. The BC mode of operation is provided on an CPUs. EC Mode
In the Ee mode, fields for channel masks 0-5, for
the interruption code, and for the instruction-length
code have been removed from the PSW, and the program-mask and condition-code fields have been
allocated different bit positions within the PSW. Two additional control bits have been introduced
into the PSW --the program-event-recording mask
and the translation-mode bit. The interruption code
and instruction-length code have been assigned sepa­
rate main-storage locations for certain classes of
interruptions, and I/O interruptions from channels 0-5 are subject to control by PSW bit 6, as well as
by channel masks in control register 2. The instruc­
tion INSERT STORAGE KEY provides the refer­
ence and change bits.
The EC mode is made available with the extended··control facility. It is specified when PSW bit 12 is one. When extended control is installed, the CPU can operate either in the BC mode or EC
mode, depending on the value of PSW bit 12. When PSW bit 112 is one and extended control is not in­
stalled, a specification exception is recognized. Programll1ling Note
The choice between BC and EC modes affects only
those aspects of operation that are specifically de­
fined to be different for the two modes. It does not
affect the operation of any facilities that are not
associated with the control bits provided in the PSW only in the EC mode, and it does not affect the va-
32 System/370 Principles of Operation tidity of any instructions. Although dynamic address
translation cannot be specified in the BC mode, the
instructions LOAD REAL ADDRESS, RESET REF­
ERENCE BIT, and PURGE TLB are valid and per­
form the specified function in the BC mode. The
instructions SET SYSTEM MASK, STORE THEN
AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK perform the specified function on
the leftmost byte of the PSW regardless of the mode
specified by the currentPSW. The instruction SET PROGRAM MASK introduces a new set of program
masks regardless of the PSW bit positions occupied
by the mask.
Set-System-Mask Suppression
When the SSM-suppression bit, bit 1 of control reg­
ister 0, is one, the execution of SET SYSTEM MASK is suppressed, and a program interruption for
a special-operation exception occurs. The initial val­
ue of the SSM-suppression bit is zero.
The SSM-suppression control, when installed, is
effective in the BC, as well as the EC, mode.
Programming Note
The facility to suppress the execution of SET SYS­
TEM MASK may be used to assist in converting a
program written for BC-mode PSW to operate with
an EC-mode PSW. Program Status Word
The program status word (PSW) contains the con­
trol information that is switched by an interruption.
Additional control and status information is con­
tained in control registers and permanently assigned
main-storage locations.
In certain circumstances all of the PSW is stored
or loaded; in others, only part of it. The entire PSW is stored and a new PSW is introduced when the CPU is interrupted. The instruction LOAD PSW introduces a new PSW; SET PROGRAM MASK
introduces a new condition code and the four pro­
gram mask bits; SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK introduce new bits into the
leftmost byte of the PSW; SET PSW KEY FROM ADDRESS introduces a new PSW key; and the in­
struction address is updated by sequential instruction
execution and replaced by successful branches. The
instruction INSERT PSW KEY stores the PSW key; STORE THEN AND SYSTEM MASK and STORE THEN OR SYSTEM MASK store the leftmost byte
of the PSW; and BRANCH AND LINK stores the
instruction-length code, condition code, program
mask, and instruction address.
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