The new PSW as introduced by an interruption or
instruction becomes active (that is, the information
introduced into the current PSW assumes control
over the system) at the completion of the interrup­
tion or at the completion of the execution of the
instructiori, respectively. The interruption for program"-event recording associated with an irlstruc­
tion that changes the PSW occurs under control of
the PSW mask that is effective at the beginning of
the operation.
The figures below show PSW formats in the BC
and EC modes.
Program Status Word Format in Be
Mode
The BC mode is specified by a zero in PSW bit posi­
tion 12. The following is a summary of the functions of the PSW fields.
Channel Masks 0-5: Bits 0-5 control whether the CPU is enabled for I/O interruptions from channels 0-5, respectively. When the bit is zero, the channel
cannot cause an 110 interruption. When the bit is
one, a condition at the channel can cause an I/O . interruption.
o Channel Masks 0-5 16
Input/Output Mask (10): Bit 6 controls whether
the CPU is enabled for I/O interruptions from chan­
nels 6 and higher. When the bit is zero, these chan­
nels cannot cause I/O interruptions. When the bit is
one, I/O interruptidns are subject to the channel-
mask bits of the corresponding channels in control
register 2: when the channel-mask bit is zero, the
channel cannot cause I/O interruption; when the
channel-mask bit is one, a condition at the channel
can cause an interruptiori.
External Mask (E): Bit 7 controls whether the CPU is enabled for interruption by conditions included in
the external class. When the bit is zero, an external
interruption cannot occur. When the bit is one, an
external interruption is subject to the corresponding
external subclass-mask bits in control register 0: when the subclass-mask bit is zero, conditions asso­
ciated with the subclass cannot cause an interrup­
tion; when the subclass-mask bit is one, an interrup­
tion in that subclass can occur.
Protection Key: Bits 8-11 form the CPU protection
key. The key is matched with a key in storage when­
ever information is stored, or whenever information
is fetched from a location that is protected against
fetching. Interruption Code
31 I nstruction Address
32 34 36 40 63 PSW Format in BC Mode
o 0 0 0 000 0 24 31 100000000 I nstruction Address
32 40 63 PSW Format in EC Mode
System Controf 33

Extended Control Mode: Bit 12 controls the format
of the PSW and the mode of operation of the CPU. When the bit is zero, the PSW format and the CPU operation are as defined for the basic control (BC)
mode. When the bit is one, the extended control
(EC) mode is specified.
Machine-,Check Mask (M): Bit 13 controls whether
the CPU is enabled for interruption by machine­
check conditions. When the bit is zero, a machine­
check int1erruption cannot occur. When the bit is
one, machine-check interruptions due to system
damage and instruction-processing damage are per­
mitted, and interruptions due to other machine­
check conditions are subject to the subclass-mask
bits in control register 14.
Wait St.,te (W): When bit 14 is one, the CPU is in
the wait state. When bit 14 is zero, the CPU is in the
running state.
Problem State (P): When bit 15 is one, the CPU is
in the problem state. When bit 15 is zero, the CPU is
in the supervisor state. Inte"uptilfJn Code: Bits 16-31 in the old PSW stored on a program, supervisor-call, external, or I/O interruption identify the cause of the interrup­
tion. When a new PSW is introduced, the contents of
this field are ignored. Instructim.-ungth Code (lLC): The code in bit
positions 32 and 33 indicates the length of the last­
interpreted instruction when a program or
supervisor-call interruption occurs or when
BRANCH AND LINK is executed. When a new PSW is introduced, the contents of this field are
ignored.
Condition Code (CC): Bits 34 and 35 are the two
bits of the condition code.
Program Mask: Bits 36-39 are the four program­
mask bits" Each bit is associated with a program
exception, as follows:
Program
Mask Bit
36
37
38
39
Program Exception
Fixed-point overflow Decimal overflow Exponent underflow Significance
When the mask bit is one, the exception results in
an interruption. When the mask bit is zero, no inter­
ruption occurs. The significance-mask bit also deter-
34 System/370 Principles of Operation mines the manner in which floating-point addition
and subtraction are completed.
Instruction Address: Bits 40-63 form the instruction
address. This address designates the location of the
leftmost byte of the next instruction.
Program Status Word Format in Ee
Mode
The EC mode is specified by a one in PSW bit posi­
tion 12. The following is a summary of the functions
of the PSW fields:
Program-Event-Recording Mask (R): Bit 1 controls
whether the CPU is enabled for interruption by pro­
gram events associated with the program-event­
recording facility. When the bit is zero, no program
event can cause an interruption. When the bit is one,
interruptions are permitted subject to the event­
mask bits in control register 9.
Translation Mode (T): Bit 5 controls whether im­
plicit translation of storage addresses by use of seg­
ment and page tables takes place. When the bit is
zero, storage addresses are not translated. When the
bit is one, the dynamic-address-translation mecha­
nism is invoked.
Input / Output Mask (10): Bit 6 controls whether
the CPU is enabled for I/O interruptions. When the
bit is zero, an I/O interruption cannot occur. When
the bit is one, I/O interruptions are subject to the
channel-mask bits in control register 2: when the
channel-mask bit is zero, the channel cannot cause
an interruption; when the channel-mask bit is one, a
condition at the channel can cause an interruption.
External Mask (E): Bit 7 controls whether the CPU is enabled for interruption by conditions included in
the external class. Its meaning is the same as in the
BC mode.
Protection Key: Bits 8-11 form the CPU protection
key. The key is matched against a key in storage
whenever information is stored, or whenever informa­
tion is fetched from a location that is protected
against fetching.
Extended-Control Mode: Bit 12 controls the format
of the PSW and the mode of operation of the CPU. When the bit is zero, the PSW format and the CPU operation are as defined for the basic-control (BC)
mode. When the bit is one, the extended-control
(EC) mode is specified.