KEY. Furthermore, program-event recording and
dynamic address translation can be specified only in
the EC mode, as the corresponding control bits in
the PSW are provided only in the EC mode.
BC Mode
In the BC mode, the PSW has the same format as in System/360, and, except for the old PSW stored on
a machine-check interruption, the interruption code
and the instruction-length code appear in the PSW. As in System/360, interruptions from channels 0-5 are subject to the control by PSW bits 0-5, and IN­
SERT STORAGE KEY provides zeros in bit posi­
tions 29 and 30 that correspond to the reference and
change bits. A number of additional permanently
assigned storage locations, however, are used during
interruptions associated with extended or new func­
tions, including those for storing the machine-check
interruption code and those for storing the monitor
code and monitor class number as the result of a
monitor-call event.
The BC mode is specified when PSW bit 12 is O. The BC mode of operation is provided on an CPUs. EC Mode
In the Ee mode, fields for channel masks 0-5, for
the interruption code, and for the instruction-length
code have been removed from the PSW, and the program-mask and condition-code fields have been
allocated different bit positions within the PSW. Two additional control bits have been introduced
into the PSW --the program-event-recording mask
and the translation-mode bit. The interruption code
and instruction-length code have been assigned sepa­
rate main-storage locations for certain classes of
interruptions, and I/O interruptions from channels 0-5 are subject to control by PSW bit 6, as well as
by channel masks in control register 2. The instruc­
tion INSERT STORAGE KEY provides the refer­
ence and change bits.
The EC mode is made available with the extended··control facility. It is specified when PSW bit 12 is one. When extended control is installed, the CPU can operate either in the BC mode or EC
mode, depending on the value of PSW bit 12. When PSW bit 112 is one and extended control is not in­
stalled, a specification exception is recognized. Programll1ling Note
The choice between BC and EC modes affects only
those aspects of operation that are specifically de­
fined to be different for the two modes. It does not
affect the operation of any facilities that are not
associated with the control bits provided in the PSW only in the EC mode, and it does not affect the va-
32 System/370 Principles of Operation tidity of any instructions. Although dynamic address
translation cannot be specified in the BC mode, the
instructions LOAD REAL ADDRESS, RESET REF­
ERENCE BIT, and PURGE TLB are valid and per­
form the specified function in the BC mode. The
instructions SET SYSTEM MASK, STORE THEN
AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK perform the specified function on
the leftmost byte of the PSW regardless of the mode
specified by the currentPSW. The instruction SET PROGRAM MASK introduces a new set of program
masks regardless of the PSW bit positions occupied
by the mask.
Set-System-Mask Suppression
When the SSM-suppression bit, bit 1 of control reg­
ister 0, is one, the execution of SET SYSTEM MASK is suppressed, and a program interruption for
a special-operation exception occurs. The initial val­
ue of the SSM-suppression bit is zero.
The SSM-suppression control, when installed, is
effective in the BC, as well as the EC, mode.
Programming Note
The facility to suppress the execution of SET SYS­
TEM MASK may be used to assist in converting a
program written for BC-mode PSW to operate with
an EC-mode PSW. Program Status Word
The program status word (PSW) contains the con­
trol information that is switched by an interruption.
Additional control and status information is con­
tained in control registers and permanently assigned
main-storage locations.
In certain circumstances all of the PSW is stored
or loaded; in others, only part of it. The entire PSW is stored and a new PSW is introduced when the CPU is interrupted. The instruction LOAD PSW introduces a new PSW; SET PROGRAM MASK
introduces a new condition code and the four pro­
gram mask bits; SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK introduce new bits into the
leftmost byte of the PSW; SET PSW KEY FROM ADDRESS introduces a new PSW key; and the in­
struction address is updated by sequential instruction
execution and replaced by successful branches. The
instruction INSERT PSW KEY stores the PSW key; STORE THEN AND SYSTEM MASK and STORE THEN OR SYSTEM MASK store the leftmost byte
of the PSW; and BRANCH AND LINK stores the
instruction-length code, condition code, program
mask, and instruction address.
The new PSW as introduced by an interruption or
instruction becomes active (that is, the information
introduced into the current PSW assumes control
over the system) at the completion of the interrup­
tion or at the completion of the execution of the
instructiori, respectively. The interruption for program"-event recording associated with an irlstruc­
tion that changes the PSW occurs under control of
the PSW mask that is effective at the beginning of
the operation.
The figures below show PSW formats in the BC
and EC modes.
Program Status Word Format in Be
Mode
The BC mode is specified by a zero in PSW bit posi­
tion 12. The following is a summary of the functions of the PSW fields.
Channel Masks 0-5: Bits 0-5 control whether the CPU is enabled for I/O interruptions from channels 0-5, respectively. When the bit is zero, the channel
cannot cause an 110 interruption. When the bit is
one, a condition at the channel can cause an I/O . interruption.
o Channel Masks 0-5 16
Input/Output Mask (10): Bit 6 controls whether
the CPU is enabled for I/O interruptions from chan­
nels 6 and higher. When the bit is zero, these chan­
nels cannot cause I/O interruptions. When the bit is
one, I/O interruptidns are subject to the channel-
mask bits of the corresponding channels in control
register 2: when the channel-mask bit is zero, the
channel cannot cause I/O interruption; when the
channel-mask bit is one, a condition at the channel
can cause an interruptiori.
External Mask (E): Bit 7 controls whether the CPU is enabled for interruption by conditions included in
the external class. When the bit is zero, an external
interruption cannot occur. When the bit is one, an
external interruption is subject to the corresponding
external subclass-mask bits in control register 0: when the subclass-mask bit is zero, conditions asso­
ciated with the subclass cannot cause an interrup­
tion; when the subclass-mask bit is one, an interrup­
tion in that subclass can occur.
Protection Key: Bits 8-11 form the CPU protection
key. The key is matched with a key in storage when­
ever information is stored, or whenever information
is fetched from a location that is protected against
fetching. Interruption Code
31 I nstruction Address
32 34 36 40 63 PSW Format in BC Mode
o 0 0 0 000 0 24 31 100000000 I nstruction Address
32 40 63 PSW Format in EC Mode
System Controf 33
Previous Page Next Page