KEY. Furthermore, program-event recording and
dynamic address translation can be specified only in
the EC mode, as the corresponding control bits in
thePSW are provided only in the EC mode.
BC Mode
In the BC mode, thePSW has the same format as in System/360, and, except for the old PSW stored on
a machine-check interruption, the interruption code
and the instruction-length code appear in thePSW. As in System/360, interruptions from channels 0-5 are subject to the control by PSW bits 0-5, and IN
SERTSTORAGE KEY provides zeros in bit posi
tions 29 and30 that correspond to the reference and
change bits. A number of additional permanently
assigned storage locations, however, are used during
interruptions associated with extended or new func
tions, including those for storing the machine-check
interruption code and those for storing the monitor
code and monitor class number as the result of a
monitor-call event.
The BC mode is specified whenPSW bit 12 is O. The BC mode of operation is provided on an CPUs. EC Mode
In the Ee mode, fields for channel masks0-5, for
the interruption code, and for the instruction-length
codehave been removed from the PSW, and the program-mask and condition-code fields have been
allocated different bit positions within thePSW. Two additional control bits have been introduced
into thePSW --the program-event-recording mask
and the translation-mode bit. The interruption code
and instruction-length code have been assigned sepa
rate main-storage locations for certain classes of
interruptions, andI/O interruptions from channels 0-5 are subject to control by PSW bit 6, as well as
bychannel masks in control register 2. The instruc
tion INSERTSTORAGE KEY provides the refer
ence and change bits.
The EC mode is made available with theextended··control facility. It is specified when PSW bit 12 is one. When extended control is installed, the CPU can operate either in the BC mode or EC
mode, depending on the value ofPSW bit 12. When PSW bit 112 is one and extended control is not in
stalled, a specification exception is recognized.Programll1ling Note
The choice between BC and EC modes affects only
those aspects of operation that are specifically de
fined to be different for the two modes. It does not
affect the operation of any facilities that are not
associated with the control bits provided in thePSW only in the EC mode, and it does not affect the va-
32System/370 Principles of Operation tidity of any instructions. Although dynamic address
translation cannot be specified in the BC mode, the
instructionsLOAD REAL ADDRESS, RESET REF
ERENCE BIT, andPURGE TLB are valid and per
form the specified function in the BC mode. The
instructions SETSYSTEM MASK, STORE THEN
ANDSYSTEM MASK, and STORE THEN OR SYSTEM MASK perform the specified function on
the leftmost byte of thePSW regardless of the mode
specified by thecurrentPSW. The instruction SET PROGRAM MASK introduces a new set of program
masks regardless of thePSW bit positions occupied
by the mask.
Set-System-Mask Suppression
When the SSM-suppressionbit, bit 1 of control reg
ister0, is one, the execution of SET SYSTEM MASK is suppressed, and a program interruption for
a special-operation exception occurs. The initial val
ue of the SSM-suppression bit is zero.
The SSM-suppression control, when installed, is
effective in the BC, as well as the EC, mode.
Programming Note
The facility to suppress the execution of SET SYS
TEMMASK may be used to assist in converting a
program written for BC-modePSW to operate with
an EC-modePSW. Program Status Word
The program status word(PSW) contains the con
trol information that is switched by an interruption.
Additional control and status information is con
tained in control registers and permanently assigned
main-storage locations.
In certain circumstances all of thePSW is stored
or loaded; in others, only part of it. The entirePSW is stored and a new PSW is introduced when the CPU is interrupted. The instruction LOAD PSW introduces a new PSW; SET PROGRAM MASK
introduces a new condition code and the four pro
gram mask bits; SETSYSTEM MASK, STORE THEN AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK introduce new bits into the
leftmost byte of thePSW; SET PSW KEY FROM ADDRESS introduces a new PSW key; and the in
struction address is updated by sequential instruction
execution and replaced by successful branches. The
instruction INSERTPSW KEY stores the PSW key; STORE THEN AND SYSTEM MASK and STORE THEN OR SYSTEM MASK store the leftmost byte
of thePSW; and BRANCH AND LINK stores the
instruction-length code, condition code, program
mask, and instruction address.
dynamic address translation can be specified only in
the EC mode, as the corresponding control bits in
the
BC Mode
In the BC mode, the
a machine-check interruption, the interruption code
and the instruction-length code appear in the
SERT
tions 29 and
change bits. A number of additional permanently
assigned storage locations, however, are used during
interruptions associated with extended or new func
tions, including those for storing the machine-check
interruption code and those for storing the monitor
code and monitor class number as the result of a
monitor-call event.
The BC mode is specified when
In the Ee mode, fields for channel masks
the interruption code, and for the instruction-length
code
allocated different bit positions within the
into the
and the translation-mode bit. The interruption code
and instruction-length code have been assigned sepa
rate main-storage locations for certain classes of
interruptions, and
by
tion INSERT
ence and change bits.
The EC mode is made available with the
mode, depending on the value of
stalled, a specification exception is recognized.
The choice between BC and EC modes affects only
those aspects of operation that are specifically de
fined to be different for the two modes. It does not
affect the operation of any facilities that are not
associated with the control bits provided in the
32
translation cannot be specified in the BC mode, the
instructions
ERENCE BIT, and
form the specified function in the BC mode. The
instructions SET
AND
the leftmost byte of the
specified by the
masks regardless of the
by the mask.
Set-System-Mask Suppression
When the SSM-suppression
ister
a special-operation exception occurs. The initial val
ue of the SSM-suppression bit is zero.
The SSM-suppression control, when installed, is
effective in the BC, as well as the EC, mode.
Programming Note
The facility to suppress the execution of SET SYS
TEM
program written for BC-mode
an EC-mode
The program status word
trol information that is switched by an interruption.
Additional control and status information is con
tained in control registers and permanently assigned
main-storage locations.
In certain circumstances all of the
or loaded; in others, only part of it. The entire
introduces a new condition code and the four pro
gram mask bits; SET
leftmost byte of the
struction address is updated by sequential instruction
execution and replaced by successful branches. The
instruction INSERT
of the
instruction-length code, condition code, program
mask, and instruction address.