event is provided to the program by means of a pro­
gram interruption, with the cause of the interruption
being idemtified in the interruption code.
Control Register Allocation
The information for controlling program-event re­
cording resides in control registers 9, 10, and 11 and
consists of the following fields:
Control Register 9: a Genera,-Re9;ste3 o 4 16 31
Control Register 10: __ __________ S_ta_rt_in_g_A_d_d_re_s_s ________ o 8 31
Control Register 11: r--I Ending Address o 8 31
PER El'l!nt Mmks: Bits 0-3 of control register 9
specify which events are monitored. The bits are
assigned as follows:
Bit 0: Successful-Branching Event
Bit 1: Instruction-Fetching Event
Bit 2: Storage-Alteration Event
Bit 3: General-Register-Alteration Event
Bits 0··3, when ones, specify that the correspond­
ing events are monitored. When the bit is zero, the
event is not monitored.
PER General-Register Masks: Bits 16-31 of control
register 9 specify which general registers are moni­
tored for alteration of their contents. The 16 bits, in
the order of ascending bit numbers, are made to
correspond one for one with the 16 registers, in the
order of ascending addresses. When the bit is one,
the register is included in monitoring for alteration;
if zero, the register is not monitored.
PER Starling Address: Bits 8-31 of control register 10 form :an address that designates the beginning of
the monitored main-storage area.
PER Elrding Address: Bits 8-31 of control register
11 form :an address that designates the end of the 40 System/370 Principles of Operation monitored main-storage area.
Programming Note
Most models operate at reduced performance while
monitoring for program events. In order to ensure
that CPU performance is not degraded due to the
operation of the program-event-recording facility,
programs that do not utilize program-event record­
ing should disable program-event recording by set­
ting the PER mask in the EC-mode PSW to zero. No
degradation due to program-event recording occurs
in the BC mode or when the PER mask in the EC­
mode PSW is zero. Disabling of program-event re­
cording in the EC mode by means of the masks and
addresses in control registers 9-11 does not neces­
sarily assure avoidance of performance degradation
due to the use of the facility.
Operation
Program-event recording (PER) is available only in
the EC mode and is under control of PSW bit 1, the PER mask; when the mask is zero, no program event
can cause an interruption; whel1 the mask is one, a
monitored event, as specified by the contents of
control registers 9, 10, and 11, causes an interrup­
tion. In BC mode the PER mask has, in effect, a
value of zero, and program-event recording is dis­
abled.
An interruption due to a program event is taken
,after the execution of the instruction responsible for
the event. The occurrence of the event does not
affect the execution of the instruction, which may be
either completed, terminated, suppressed, or nulli­
fied.
A program-event condition cannot be kept pend­
ing. When the CPU is disabled for a particular pro­
gram event at the time it occurs, either by the mask
in the PSW or by the masks in control register 9, the
interruption condition is lost.
A change to the PER mask in the PSW or to the PER control fields in control registers 9, 10, and 11
affects program-event recording starting with the
execution of the immediately following instruction.
When the CPU is enabled for some program event
and an instruction causes the CPU to be disabled for
that particular event, the event causes an interrup­
tion if it occurs during the execution of the instruc­
tion.
When LOAD PSW or SUPERVISOR CALL
causes a PER condition and at the same time
changes CPU operation from EC mode to BC mode,
the PER interruption is taken with the old PSW specifying BC mode and with the interruption code
stored in the old PSW. The additional information
identifying the PER condition is stored in its regular
format in locations 150-155. Program-event recording applies to all instruc­
tions, including the special-purpose instructions,
such as those provided for emulation. The latter
class of instructions indicates all events that have
occurred and may additionally indicate events that
did not occur and were not called for in the instruc­
tion, provided monitoring was enabled for the type
of event by the PER mask in the PSW and the PER event masks, bits 0-3 in control register 9. In such
cases, the contents of the remaining positions in
control registers 9, 10, and 11 may be ignored. Thus,
for example, a special-purpose instruction may cause
general-register alteration to be indicated even
though no general registers are altered, and even . though bits 16-31 of control register 9 are all zeros.
Identification of Cause
The cause of the interruption is identified by setting
bit 8 of the interruption code to one and by the in­
formation placed in locations 150-155 of main stor­
age. The interruption code on a program-event inter­
ruption may indicate concurrently a program event
and another program-interruption condition. The
format of the information stored in locations 150- 155 is as follows:
Locations 150-151: I P.C. 1000000000000 1 o 4 15
Locations 152-155: 1000000001 o 8
PER Address
31
The event causing a program-event interruption is
identified by a one in bit positions 0-3 of location 150, the PER code, with the rest of the bits in the
code set to zeros. The bit position in the PER code
for a particular event is the same as the bit position
for that event in the PER event-mask field. When a PER interruption occurs and more than one desig­
nated program event has been recognized, all recog­
nized program events are concurrently indicated in
the PER code.
The PER address at locations 153-155 identifies
the location of the instruction causing the event.
When the instruction is executed by means of EX­
ECUTE, the address of the location containing the
EXECUTE instruction is placed in the PER-address
field. In either case, the address of the instruction to
be executed next is placed in the PSW. Zeros are
stored in bit positions 4-7 of location 150 and at
locations 151 and 152.
Priority of Indication
When the execution of an interruptible instruction is
due to be interrupted by an I/O, external, or
machine-check-recovery condition, the program­
event interruption occurs first, and the I/O, external,
or machine-check interruption is subsequently sub­
ject to the control of mask bits in the new PSW. Similarly, when the CPU is placed in the stopped
state during the execution of an interruptible instruc­
tion, an interruption for a pending PER condition
occurs before the stopped state is entered. When a
dynamic-address-translation (DAT) exception is
encountered, the pending PER condition is indicated
concurrently with the DAT condition. Normally a
program event does not cause premature interrup­
tion of the interruptible instruction unless some oth­
er event is due to cause an asynchronous interrup­
tion. However, depending on the model, in certain
situations, a PER condition may cause the execution
of an interruptible instruction to be interrupted with­
out an associated asynchronous condition or pro­
gram exception.
In the case of an instruction-fetching event on SUPERVISOR CALL, the PER interruption occurs
immediately after the supervisor-call interruption.
Programming Notes
In the following cases an instruction can both cause
a PER interruption and change the value of bits con­
trolling the occurrence of a PER interruption for
that particular event. In these cases the original val­
ues of the control bits determine whether a PER interruption occurs.
t. The instructions LOAD PSW, SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and SUPERVISOR CALL can cause
an instruction-fetching event and disable the CPU for PER interruptions. Additionally, STORE THEN AND SYSTEM MASK can
cause storage alteration to be indicated. In all
these cases, the old program PSW associated
with the program-event interruption may indi­
cate that the CPU was disabled for the inter­
ruption.
2. The instruction LOAD CONTROL may cause
an instruction-fetching event and change the
value of the PER event masks in control regis­
ter 9 or the addresses in control registers 10 and 11 controlling indication of the instruction­
fetching event.
System Control 41
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