No instructions can both change the values of
general-register alteration masks and cause a
general-register alteration event to be recognized.
When a PER interruption occurs during the execu­
tion of an interruptible instruction, the ILC indi­
cates length of that instruction or EXECUTE, as
appropriate. When a PER interruption occurs as a
result of LOAD PSW or SUPERVISOR CALL, the
ILC indicates the length of these instructions or EX­
ECUTE, as appropriate, unless a concurrent specifi­
cation exception on LOAD PSW calls for an ILC of O. When a PER interruption is caused by branching,
the PER address identifies the branch instruction (or
EXECUTE, as appropriate), whereas the old PSW points to the next instruction to be executed. When
the interruption occurs during the execution of an
interruptible instruction, the PER address and the
instruction address in the old PSW are the same.
Storage Area Designation
Two of the program events--instruction fetching and
storage alteration--involve the designation of an area
in main storage. The storage area monitored for the
references starts at the location designated by the
starting address in control register 10 and extends up
to and including the location designated by the end­
ing address in control register 11. The area extends
to the right of the starting address.
When dynamic address translation is specified,
the storage area is designated by logical when dynamic address translation is suppressed,
control registers 10 and 11 contain real addresses.
The s,et of locations designated for monitoring
purposes wraps around at location 16,777,215; that
is, location 0 is considered to follow location
16,777,215. When the starting address is smaller
than the ending address, the area is contiguous.
When the starting address is larger than the ending
address, the set of locations designated for monitor­
ing purposes includes the area from the starting ad­
dress to the largest address in the system and the
area from location 0 to, and including, the ending
address. When the starting address is equal to the
ending address, only the location designated by that
address is monitored.
The monitoring of main-storage alteration and
instruction fetching is performed by carrying out the
address on all 24 bits of the addresses. Events
Successful Branching
Execution of a successful branch operation causes a
program-event interruption if bit 0 of the PER- 42 System/370 Principles of Operation
event-mask field is one and the PER mask in the PSW is one.
A successful branch occurs whenever one of the
following instructions causes control to be passed to
the instruction designated by the branch address:
BRANCH ON CONDITION BRANCH AND LINK
BRANCH ON COUNT BRANCH ON INDEX HIGH
BRANCH ON INDEX LOW OR EQUAL
The branch event is also indicated by special-
purpose instructions, such as those provided for em­
ulation, when the special-purpose instruction causes
a branch. That is, the location of the next instruc­
tion executed by the CPU after leaving emulation
mode does not immediately follow the location of
the instruction which caused the CPU to enter the
mode.
The event is identified by setting bit 0 of the PER code to one.
Instruction Fetching
Fetching the first byte of an instruction from the
main-storage area designated by the contents of
control registers 10 and 11 causes a program-event
interruption if bit 1 of the PER-event-mask field is
one and the PER mask in the PSW is one.
A program event is recognized whenever the CPU executes an instruction whose initial byte is located
within the monitored area. When the instruction is
executed by means of EXECUTE, a program event
is recognized when the first byte of the EXECUTE
instruction or the subject instruction or both is locat­
ed in the monitored area.
The event is identified by setting bit 1 of the PER code to one.
Storage Alteration
Storing of data by the CPU in the main-storage area
designated by the contents of control registers 10 and 11 causes a program-event interruption if bit 2
of the PER-event-mask field is one and the PER mask in the PSW is one.
The contents of main storage are considered to
have been altered whenever the CPU executes an
instruction that causes the whole operand or part of
it to be stored within the monitored area of main
storage. Alteration is considered to take place when­
ever storing is considered to take place for purposes
of indicating protection exceptions. (See "Recognition of Access Exceptions" in the chapter
"Interruptions. ") An arithmetic or movement opera­
tion is considered to fetch the operand, perform the
indicated operation, if any, and then store the result. Such storing into main storage constitutes alteration

for program-event recording purposes even if the
value stored is the same as the original value.
Implied locations that are referred to by the CPU in the process of timer updating, interruptions, exe­
cution of 110 instructions, and machine-check logout,
including the interval timer, PSW, CSW, and logout
locations, are not monitored. These locations, how­
ever, are monitored when information is stored there
explicitly by an instruction. Similarly, monitoring
does not apply to storing of data by a channel. The
key storage is not considered part of main storage,
and hence monitoring does not apply to alterations
made by SET STORAGE KEY and RESET REF­
ERENCEBIT.
The instruction STORE CHARACTERS UN­ DER MASK is not considered to alter the storage
location when the mask is zero.
The instructions COMPARE AND SWAP and COMP ARE DOUBLE AND SWAP are considered
to alter the second-operand location only when stor­
ing actually occurs.
The event is identified by setting bit 2 of the PER code to one.
General-Register Alteration
Alteration of the contents of a general register caus­
es a program-event interruption if bit 3 of the PER­ event-mask field is one, the alteration mask corre­
sponding to that general register is one, and the PER mask in the PSW is one.
The contents of a general register are considered
to have been altered whenever a new value is placed
into the register. Recognition of the event is not
contingent on the new value being different from the
previous one. A register-to-register format arithme­
tic or movement operation is considered to fetch the
contents of the register, perform the indicated opera­
tion, if any, and then replace the value in the regis­
ter. The register can be designated implicitly, such as
in TRANSLATE AND TEST and EDIT AND
MARK, or explicitly by an RR, RX, or RS instruc­
tion, including BRANCH AND LINK, BRANCH ON COUNT, BRANCH ON INDEX HIGH, and
BRANCH ON INDEX LOW OR EQUAL.
The instructions EDIT AND MARK and TRANS­
LATE AND TEST are considered to have altered
the contents of general register 1 only when these
instructions have caused information to be stored
into the register.
The instructions MOVE LONG and COMPARE LOGICAL LONG are always considered to alter the
contents of the four registers specifying the two op,er­ ands, including the cases where the padding charac­
ter is used, when both operands have a zero length,
or when condition code 3 is set for MOVE LONG. The instruction INSERT CHARACTERS UN­ DER MASK is not considered to alter the general
register when the mask is zero.
The instructions COMPARE AND SWAP and COMP ARE DOUBLE AND SWAP are considered
to alter the general register, or general register pair,
designated by Rl only when the contents are actual­
ly replaced, that is, when the first and second oper­
ands are not equal.
The event is identified by setting bit 3 of the PER code to one.
Programming Notes
The following are some specifics concerning general­
register alteration:
1. Register-to-register load instructions are con­
sidered to alter the register contents even when
both operand addresses designate the same
register.
2. Addition or subtraction of zero and multiplica­
tion or division by one are considered to con­
stitute alteration.
3. Logical and fixed-point shift operations are
considered to alter the register contents even
for shift amounts of zero.
4. The branching instructions BXH and BXLE
are considered to alter the first operand even
when zero is added to its value.
Indication of Events Concurrently with Other Interruption Conditions
The following rules govern the indication of program
events caused by an instruction that has caused also
a program exception or the monitor event to be indi­
cated, or that causes a supervisor-call interruption.
1. The indication of an instruction-fetching event
does not depend on whether the execution of
the instruction was completed, terminated, sup­
pressed, or nullified. The event, however, is not
indicated when an access exception prohibits
access to the first byte of the instruction.
When the first halfword of the instruction is
accessible but an access exception applies to
the second or third halfword of the instruction,
it is unpredictable whether the instruction­
fetching event is indicated.
2. When the operation is completed, the event is
indicated regardless of whether any program
exception or the monitoring event is recog­
nized.
3. Successful branching, storage alteration, or
general-register alteration are not indicated for
an operation or, in the case of the interruptible
System Control 43