Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 In a multiprocessing system, each CPU has a sep­
arate clock comparator.
The clock comparator has the same format as the
time-of-day clock. In the basic form, the clock com­
parator consists of bits 0-47, which are compared
with the corresponding bits of the time-of-day clock.
In some models, higher resolution is obtained by
comparing more than 48 bits. When the resolution of
the time-of -day clock is less than that of the clock
comparator, the contents of the clock comparator
are compared with the clock value as this value
would be stored by STORE CLOCK. Thli! clock comparator causes an external inter­
ruption with the interruption code 1004 (hex). A re­
quest for a clock comparator interruption exists when­
ever either of the following conditions exists: • The time-of -day clock is running and the value
of the clock comparator is less than the value
in the compared portion of the time-of-day
dock, both comparands being considered bina­
ry unsigned quantities • The clock comparator is installed and the time­ of -day clock is in the error state or not opera­ Honal A request for a clock-comparator interruption
does not remain pending when the value of the clock
comparator is made equal to or larger than that of
the time-of -day clock or when the value of the time­
of-day clock is made less than the clock-comparator
value.. The latter may occur as a result of the time­
of-day clock either being set or wrapping to zero.
The clock comparator can be inspected by means
of the: instruction STORE CLOCK COMP ARA­ TOR and can be set to a specific value by means of
the SET CLOCK COMPARATOR instruction.
The contents of the clock comparator are initial­
ized to zero.
Programming Note
The instruction STORE CLOCK may store a value
which is larger than that in the clock comparator,
even though the CPU is enabled for the clock com­
parator interruption. This is because the time-of-day
clock: may be incremented one or more times be­
tween the instants when instruction execution is
begun and when the clock value is accessed. Howev­
er, in this situation the interruption occurs at the
completion of the execution of the instruction.
An interruption request for clock comparator
persists as long as the clock comparator value is less
than that of the TOO clock or as long as the TOO clock is not operational or in the error state. In view
of this, after an external interruption for clock com­
parator has occurred, either the value of the clock
comparator has to be replaced or the clock-
48 System/370 Principles of Operation comparator submask has to be set to zero before the CPU is again enabled for external interruptions. Otherwise, loops of external interruptions are
formed. CPU Timer
The CPU timer provides a means for measuring
elapsed CPU time and for causing an interruption
when a prespecified amount of time has elapsed.
In a multiprocessing system, each CPU has a sep­
arate CPU timer.
The CPU timer is a binary counter with a format
which is the same as that of the time-of -day clock,
except that bit 0 is considered a sign. In the basic
form, the CPU timer is decremented by subtracting a
one in bit position 51 every microsecond. In models
having a higher or lower resolution, a different bit
position is decremented at such a frequency that the
rate of reduction of the CPU timer is the same as if a
one were subtracted in bit position 51 every micro­
second. The resolution of the CPU timer is such that
the stepping rate is comparable to the instruction
execution rate of the model.
The CPU timer causes an external interruption
with the interruption code 1005 (hex). A request for
a CPU-timer interruption exists whenever the value
in the CPU timer is negative (bit 0 of the CPU timer
is one). The request does not remain pending when
the CPU-timer value is made positive.
When both the CPU timer and the time-of -day
clock are running, the stepping rates are synchro­
nized such that both are stepped at the same rate.
Normally the decrementing of the CPU timer is not
affected by concurrent I/O activity. However, in
some models the CPU timer may stop during ex­
treme I/O activity and other similar interference
situations. In these cases, the time recorded by the CPU timer provides a more accurate measure of the CPU time used by the program than that which
would have been recorded had the CPU timer con­
tinued to step.
The CPU timer is decremented when the CPU is
executing instructions, during the wait state, and
during initial program loading, but it is not decre­
mented when the CPU is in the stopped state. When
the rate switch on the system console is in the
instruction-step position, the CPU timer is decre­
mented only during the time in which the CPU is
actually performing a unit of operation. Depending
on the model, the CPU timer mayor may not be
decremented when the time-of -day clock is in the
error, stopped, or not-operational state or when the CPU is in the check-stop state.
The CPU timer can be inspected by means of the
instruction STORE CPU TIMER and can be set to a

specific value by means of the SET CPU TIMER
instruction.
The contents of the CPU timer are initialized to
zero.
Programming Notes
The instruction STORE CPU TIMER may store a
negative value even though the CPU is enabled for
the interruption. This is because the timer value may
be decremented one or more times between the in­
stants when instruction execution is begun and when
the CPU timer is accessed. However, in this situation
the interruption occurs at the completion of the ex­
ecution of the instruction.
The fact that a CPU-timer interruption does not
remain pending when the CPU timer is set to a posi­
tive value eliminates the problem of an undesired
interruption. This would occur if between the time
that the old value is stored and a new value is set the CPU is disabled and the CPU-timer value goes from
positive to negative.
The fact that CPU-timer interruptions are re­
quested whenever the CPU timer is negative rather
than just when the timer goes from positive to nega­
tive eliminates the requirement to test a value to
ensure that it is positive before setting the CPU tim­
er. A previously stored CPU-timer value could be
negative if the CPU timer goes from positive to neg­
ative while external interruptions are disallowed
between the time a non-CPU-timer interruption is
taken and the CPU timer is stored.
The persistence of the CPU timer interruption
request means, however, that after an external inter­
ruption for CPU timer has occurred, either the value
of the CPU timer has to be replaced or the CPU timer submask has to be set to zero before the CPU is again enabled for external interruptions. Other­ wise, loops of external interruptions are formed.
The CPU timer in association with a program may
be used as both a CPU-execution-time clock and a CPU interval timer.
The time measured for the execution of a se­
quence of instructions may depend on the effects of
such factors as I/O interference, the remoteness of
storage, and use of the cache, dynamic address
translation, and instruction retry. Hence, repeated
measurements of the same sequence on the same
installation may differ.
Interval Timer
The interval timer occupies a 32-bit word at real
main-storage location 80 and has the following for­
mat:
o 24
In a multiprocessing system, each CPU has an
associated interval timer.
31
The interval timer is a binary counter that is treat­
ed as a signed integer by following the rules for
fixed-point arithmetic. In the basic form, the con­
tents of the timer are reduced by one in bit position
23 every 1/300 of a second. Higher resolution of
timing may be obtained in some models by counting
with higher frequency in one of the positions 24
through 31. In each case, the frequency is adjusted
to give counting at 300 cycles per second in bit posi­
tion 23. The cycle of the timer is approximately 15.5
hours.
The interval timer causes an external interruption,
with bit 8 of the interruption code set to one and bits 0-7 set to zero. Bits 9-15 are zero unless set to one
for another condition that is concurrently indicated.
A request for an interval-timer interruption is
generated whenever the timer value is decremented
from a positive number, including zero, to a negative
number. The request is preserved and remains pend­
ing in the CPU until it is cleared by an interval-timer
interruption or reset. The overflow occurring as the
timer value is decremented from a large negative'
number to a large positive number is ignored.
The timer is not necessarily synchronized with
line frequency or the time-of -day clock, and its tol­
erance is not necessarily related to the tolerance of
the line frequency or the clock.
The timer contents are updated at the appropriate
frequency whenever other activity in the system
permits it. The updating occurs only between the
execution of instructions, with the exception that the
timer may be updated during the execution of an
interruptible instruction, such as MOVE LONG. An
updated timer value is normally available at the end
of each instruction execution. When the execution of
an instruction or other activity in the system causes
updating to be delayed by more than one period, the
contents of the timer may be reduced by more than
one unit in a single updating cycle, depending on the
length of the delay and the extent of timer backup
storage. Timer updating may be omitted when I/O data transmission approaches the limit of storage
capability, when a channel sharing CPU equipment
and operating in burst mode causes CPU activity to
be locked out, or when the instruction time for
READ DIRECT is excessive. The program is not
alerted when omission of updating causes the real­
time count to be lost. System Control 49