specific value by means of the SET CPU TIMER
instruction.
The contents of theCPU timer are initialized to
zero.
Programming Notes
The instructionSTORE CPU TIMER may store a
negative value even though theCPU is enabled for
the interruption. This is because the timer value may
be decremented one or more times between the in
stants when instruction execution is begun and when
theCPU timer is accessed. However, in this situation
the interruption occurs at the completion of the ex
ecution of the instruction.
The fact that a CPU-timer interruption does not
remain pending when theCPU timer is set to a posi
tive value eliminates the problem of an undesired
interruption. This would occur if between the time
that the old value is stored and a new value is set theCPU is disabled and the CPU-timer value goes from
positive to negative.
The fact that CPU-timer interruptions are re
quested whenever theCPU timer is negative rather
than just when the timer goes from positive to nega
tive eliminates the requirement to test a value to
ensure that it is positive before setting theCPU tim
er. A previously stored CPU-timer value could be
negative if theCPU timer goes from positive to neg
ative while external interruptions are disallowed
between the time a non-CPU-timer interruption is
taken and theCPU timer is stored.
The persistence of theCPU timer interruption
request means, however, that after an external inter
ruption forCPU timer has occurred, either the value
of theCPU timer has to be replaced or the CPU timer submask has to be set to zero before the CPU is again enabled for external interruptions. Other wise, loops of external interruptions are formed.
TheCPU timer in association with a program may
be used as both a CPU-execution-time clock and aCPU interval timer.
The time measured for the execution of a se
quence of instructions may depend on the effects of
such factors asI/O interference, the remoteness of
storage, and use of the cache, dynamic address
translation, and instruction retry. Hence, repeated
measurements of the same sequence on the same
installation may differ.
Interval Timer
The interval timer occupies a 32-bit word at real
main-storage location80 and has the following for
mat:
o 24
In a multiprocessing system, eachCPU has an
associated interval timer.
31
The interval timer is a binary counter that is treat
ed as a signed integer by following the rules for
fixed-point arithmetic. In the basic form, the con
tents of the timer are reduced by one in bit position
23 every1/300 of a second. Higher resolution of
timing may be obtained in some models by counting
with higher frequency in one of the positions 24
through 31. In each case, the frequency is adjusted
to give counting at300 cycles per second in bit posi
tion 23. The cycle of the timer is approximately 15.5
hours.
The interval timer causes an external interruption,
with bit 8 of the interruption code set to one and bits0-7 set to zero. Bits 9-15 are zero unless set to one
for another condition that is concurrently indicated.
A request for an interval-timer interruption is
generated whenever the timer value is decremented
from a positive number, including zero, to a negative
number. The request is preserved and remains pend
ing in theCPU until it is cleared by an interval-timer
interruption or reset. The overflow occurring as the
timer value is decremented from a large negative'
number to a large positive number is ignored.
The timer is not necessarily synchronized with
line frequency or the time-of -day clock, and its tol
erance is not necessarily related to the tolerance of
the line frequency or the clock.
The timer contents are updated at the appropriate
frequency whenever other activity in the system
permits it. The updating occurs only between the
execution of instructions, with the exception that the
timer may be updated during the execution of an
interruptible instruction, such asMOVE LONG. An
updated timer value is normally available at the end
of each instruction execution. When the execution of
an instruction or other activity in the system causes
updating to be delayed by more than one period, the
contents of the timer may be reduced by more than
one unit in a single updating cycle, depending on the
length of the delay and the extent of timer backup
storage. Timer updating may be omitted whenI/O data transmission approaches the limit of storage
capability, when a channel sharingCPU equipment
and operating in burst mode causesCPU activity to
be locked out, or when the instruction time for
READ DIRECT is excessive. The program is not
alerted when omission of updating causes the real
time count to be lost.System Control 49
instruction.
The contents of the
zero.
Programming Notes
The instruction
negative value even though the
the interruption. This is because the timer value may
be decremented one or more times between the in
stants when instruction execution is begun and when
the
the interruption occurs at the completion of the ex
ecution of the instruction.
The fact that a CPU-timer interruption does not
remain pending when the
tive value eliminates the problem of an undesired
interruption. This would occur if between the time
that the old value is stored and a new value is set the
positive to negative.
The fact that CPU-timer interruptions are re
quested whenever the
than just when the timer goes from positive to nega
tive eliminates the requirement to test a value to
ensure that it is positive before setting the
er. A previously stored CPU-timer value could be
negative if the
ative while external interruptions are disallowed
between the time a non-CPU-timer interruption is
taken and the
The persistence of the
request means, however, that after an external inter
ruption for
of the
The
be used as both a CPU-execution-time clock and a
The time measured for the execution of a se
quence of instructions may depend on the effects of
such factors as
storage, and use of the cache, dynamic address
translation, and instruction retry. Hence, repeated
measurements of the same sequence on the same
installation may differ.
Interval Timer
The interval timer occupies a 32-bit word at real
main-storage location
mat:
o 24
In a multiprocessing system, each
associated interval timer.
31
The interval timer is a binary counter that is treat
ed as a signed integer by following the rules for
fixed-point arithmetic. In the basic form, the con
tents of the timer are reduced by one in bit position
23 every
timing may be obtained in some models by counting
with higher frequency in one of the positions 24
through 31. In each case, the frequency is adjusted
to give counting at
tion 23. The cycle of the timer is approximately 15.5
hours.
The interval timer causes an external interruption,
with bit 8 of the interruption code set to one and bits
for another condition that is concurrently indicated.
A request for an interval-timer interruption is
generated whenever the timer value is decremented
from a positive number, including zero, to a negative
number. The request is preserved and remains pend
ing in the
interruption or reset. The overflow occurring as the
timer value is decremented from a large negative'
number to a large positive number is ignored.
The timer is not necessarily synchronized with
line frequency or the time-of -day clock, and its tol
erance is not necessarily related to the tolerance of
the line frequency or the clock.
The timer contents are updated at the appropriate
frequency whenever other activity in the system
permits it. The updating occurs only between the
execution of instructions, with the exception that the
timer may be updated during the execution of an
interruptible instruction, such as
updated timer value is normally available at the end
of each instruction execution. When the execution of
an instruction or other activity in the system causes
updating to be delayed by more than one period, the
contents of the timer may be reduced by more than
one unit in a single updating cycle, depending on the
length of the delay and the extent of timer backup
storage. Timer updating may be omitted when
capability, when a channel sharing
and operating in burst mode causes
be locked out, or when the instruction time for
READ DIRECT is excessive. The program is not
alerted when omission of updating causes the real
time count to be lost.