specific value by means of the SET CPU TIMER
instruction.
The contents of the CPU timer are initialized to
zero.
Programming Notes
The instruction STORE CPU TIMER may store a
negative value even though the CPU is enabled for
the interruption. This is because the timer value may
be decremented one or more times between the in­
stants when instruction execution is begun and when
the CPU timer is accessed. However, in this situation
the interruption occurs at the completion of the ex­
ecution of the instruction.
The fact that a CPU-timer interruption does not
remain pending when the CPU timer is set to a posi­
tive value eliminates the problem of an undesired
interruption. This would occur if between the time
that the old value is stored and a new value is set the CPU is disabled and the CPU-timer value goes from
positive to negative.
The fact that CPU-timer interruptions are re­
quested whenever the CPU timer is negative rather
than just when the timer goes from positive to nega­
tive eliminates the requirement to test a value to
ensure that it is positive before setting the CPU tim­
er. A previously stored CPU-timer value could be
negative if the CPU timer goes from positive to neg­
ative while external interruptions are disallowed
between the time a non-CPU-timer interruption is
taken and the CPU timer is stored.
The persistence of the CPU timer interruption
request means, however, that after an external inter­
ruption for CPU timer has occurred, either the value
of the CPU timer has to be replaced or the CPU timer submask has to be set to zero before the CPU is again enabled for external interruptions. Other­ wise, loops of external interruptions are formed.
The CPU timer in association with a program may
be used as both a CPU-execution-time clock and a CPU interval timer.
The time measured for the execution of a se­
quence of instructions may depend on the effects of
such factors as I/O interference, the remoteness of
storage, and use of the cache, dynamic address
translation, and instruction retry. Hence, repeated
measurements of the same sequence on the same
installation may differ.
Interval Timer
The interval timer occupies a 32-bit word at real
main-storage location 80 and has the following for­
mat:
o 24
In a multiprocessing system, each CPU has an
associated interval timer.
31
The interval timer is a binary counter that is treat­
ed as a signed integer by following the rules for
fixed-point arithmetic. In the basic form, the con­
tents of the timer are reduced by one in bit position
23 every 1/300 of a second. Higher resolution of
timing may be obtained in some models by counting
with higher frequency in one of the positions 24
through 31. In each case, the frequency is adjusted
to give counting at 300 cycles per second in bit posi­
tion 23. The cycle of the timer is approximately 15.5
hours.
The interval timer causes an external interruption,
with bit 8 of the interruption code set to one and bits 0-7 set to zero. Bits 9-15 are zero unless set to one
for another condition that is concurrently indicated.
A request for an interval-timer interruption is
generated whenever the timer value is decremented
from a positive number, including zero, to a negative
number. The request is preserved and remains pend­
ing in the CPU until it is cleared by an interval-timer
interruption or reset. The overflow occurring as the
timer value is decremented from a large negative'
number to a large positive number is ignored.
The timer is not necessarily synchronized with
line frequency or the time-of -day clock, and its tol­
erance is not necessarily related to the tolerance of
the line frequency or the clock.
The timer contents are updated at the appropriate
frequency whenever other activity in the system
permits it. The updating occurs only between the
execution of instructions, with the exception that the
timer may be updated during the execution of an
interruptible instruction, such as MOVE LONG. An
updated timer value is normally available at the end
of each instruction execution. When the execution of
an instruction or other activity in the system causes
updating to be delayed by more than one period, the
contents of the timer may be reduced by more than
one unit in a single updating cycle, depending on the
length of the delay and the extent of timer backup
storage. Timer updating may be omitted when I/O data transmission approaches the limit of storage
capability, when a channel sharing CPU equipment
and operating in burst mode causes CPU activity to
be locked out, or when the instruction time for
READ DIRECT is excessive. The program is not
alerted when omission of updating causes the real­
time count to be lost. System Control 49
The value of the timer is accessible by fetching
the word at location 80 as an operand, provided the
location is not protected against fetching. The 32-bit
timer value may be changed at any time by storing a
new value at location 80. When location 80 is pro­
tected, any attempt to change the value of the timer
causes a program interruption for protection excep­
tion. When protection exception is indicated, the
timer value remains unchanged.
The value of the timer may be changed without
losing the real-time count by loading the new value
in byte locations 84-87 and then shifting bytes 80- 87 into byte locations 76-83 by means of the in­
struction MOVE (MVC), thus placing in a single
operation the new timer value into word location 80 and making the old value available at location 76.
The MVC instruction may designate locations 76-87
by real addresses 76-87 or by any logical addresses
that translate to real addresses 76-87.
When the contents of the timer are fetched by
another CPU or by a channel or are used as a source
of an instruction, the result is unpredictable. Similar­
ly, storing by the channel or by another CPU at loca­
tion 80 causes the contents of the timer to be unpre­
dictable.
The timer value is not decremented when the CPU is not in the operating state, or when the rate
switch 0111 the system console is set to the
instruction-step position.
Programming Notes
The interval timer, in association with a program,
can serve both as a real-time clock and as an interval
timer.
If any means other than the instruction MOVE (MVC) are used to interrogate and then replace the
value of the timer, including MOVE LONG or two
separate instructions, the program may lose a time
increment if an updating cycle occurs between fetch­
ing and storing.
When the value of the interval timer is to be re­
corded on an 110 device, the program should first
store the timer value in a temporary storage location
to which the 110 operation subsequently refers.
When the channel fetches the timer value directly
from location 80, the value obtained is unpredicta­
ble.
Externally Initiated Functions
Resets
Two types of CPU-reset functions are provided: CPU reset and initial CPU reset. By combining the
two CPU-reset functions with the I/O-system-reset
function and clearing of storage, the following three
system resets are provided: program reset, initial
program reset, and system-clear reset. The table "Manual Initiation of System Resets" at the end of
the description of resets summarizes how each type
of system reset is manually initiated. Power-on reset
is performed as part of powering on. CPU reset provides a means of clearing
equipment-check indications and the resultant un­
predictability, if any, in the CPU state with the least
amount of information destroyed. It is intended in
particular for clearing check conditions when the
system state is to be preserved for analysis or re­
sumption of the operation.
Initial CPU reset performs the same functions as CPU reset but additionally initializes the contents of
control fields. In particular, it initializes the prefix
and control registers, which is normally necessary for
initial program loading.
Function Performed On 1
Position of Enable- CPU on Which Key Was Other CPUs Configured for
Propagation of Manual Reset Key Activated System-Clear Key Activated System reset Without store-status facility Normal Initial-program reset With store-status facility Normal Program reset Program reset System reset Clf!ar System-clear reset System-clear reset
Load Normal I nitial-program reset, followed Program reset
by IPL Load Clear System-clear reset, followed System-clear reset
by IPL Explanation: * This situation cannot occur, since the store-status facility is provided in a CPU equipped for multiprocessing.
1 Activation of the system-reset or load key may change the configuration, including the connection with channels, storage units,
and other CPUs.
Manual Initiation of System Resets 50 System/370 Principles of Operation
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