Program reset and initial program reset cause CPU reset and initial CPU reset, respectively, to be
performed, and additionally cause I/O system reset
to be performed. Sy.rtem-clear reset causes initial program reset to
be performed and, additionally, initializes or clears
all registers and storage locations whose contents
can be modified by a program. Such clearing is use­
ful in debugging programs and to ensure user priva­
cy.
Power-on reset initializes the contents of all con­
trol fields and either clears to zeros with valid
checking-block code, or introduces valid checking­
block code on, registers and storage locations that
lose their contents when power is down. It eliminates
the possibility of machine-check conditions due to
random values introduced by powering on. CPU Reset CPU reset causes the following actions:
1. The execution of the current instruction or
other processing sequence, such as interrup­
tion, is terminated, and all program and
supervisor-call interruption conditions are
cleared.
2. Pending external-interruption conditions are
cleared.
3. Pending machine-check-interruption conditions
and error indications are cleared.
4. The translation-lookaside buffer is cleared of
entries.
5. Any buffers containing prefetched instructions
or operands or results due to be stored are
cleared of entries.
6. The CPU is placed in the stopped state after
actions 1-5 have been completed. See the table "Summary of Reset Action" for a
detailed description of the effect of this reset on
other parts of the system.
The CPU-reset function is performed as part of
the three system resets and when the CPU accepts
the CPU-reset order specified by a SIGNAL PROC­ ESSOR instruction addressing this CPU. On some CPUs, model-dependent controls may be provided
for initiating CPU reset.
Initial CPU Reset
Initial CPU reset causes CPU reset to be performed
and additionally causes the following actions prior to
placing the CPU in the stopped state:
1. The contents of the PSW, prefix, CPU timer,
and clock comparator are set to zeros with
valid checking-block code.
2. The contents of control registers are set to their
initial values with valid checking-block code.
By setting the contents of the PSW to zero, the
initial-CPU-reset function causes the PSW to assume
the BC-mode format. The contents of the
instruction-length-code and interruption-code fields
remain unpredictable, as these values are not re­
tained when a new PSW is introduced. See the table "Summary of Reset Action" for a
detailed description of the effect of this reset on
other parts of the system.
The initial-CPU-reset function is performed as
part of the initial-program and system-clear resets
and when the CPU accepts the initial-CPU-reset
order specified by a SIGNAL PROCESSOR instruc­
tion addressing this CPU. On some CPUs, model­
dependent controls may be provided for initiating
initial CPU reset. I/O System Reset I/O system reset causes the I/O-system-reset func­
tion to be performed in the channel (see the chapter "I/O Operations"). As part of this reset, pending
I/O-interruption conditions are cleared and system
reset is signaled to all control units and devices con­
figured to the channel.
The effect of system reset on I/O control units
and devices and the resultant control-unit and device
state are described in the appropriate Systems Refer­
ence Library (SRL) or System Library (SL) publica­
tion. In general, a system reset resets only those
functions in a shared control unit or device that are
associated with the CPU signaling the reset.
The I/O-system-reset function is performed as
part of the three system resets and normally cannot
be initiated by itself.
Program Reset Program reset causes CPU reset to be performed
and causes I/O system reset to be performed in all
channels configured to the CPU. See the table "Summary of Reset Action" for a detailed descrip­
tion of the effect of the reset on other parts of the
system.
Execution of the program-reset function is initiat­
ed in a CPU by any of the following:
1. On a model that has the store-status facility
installed, by activating the system-reset key on
that CPU with the enable-system-clear key in
the normal position.
2. By activating the following keys in any other
configured CPU in a multiprocessing system: • The system-reset key with the enable-system­
clear key in the normal position, or
System Control 51

• The ]load key with the enable-system-clear
key in the normal position.
3. When lthe CPU accepts the program-reset or­
der specified by a SIGNAL PROCESSOR in­
struction addressing this CPU. Initial Program Reset
Initial program reset causes initial CPU reset to be
performed and causes I/O system reset to be per­
formed in all channels configured to the CPU. See the table "Summary of Reset Action" for a detailed
description of the effect of the reset on other parts
of the system.
Reset Function CPU Program Initial CPU Initial Program System Clear Power On Area Affected Reset Reset CPU state S S Configured channels N
R PSW U/V U/V Prefix U/V utv CPU timer UN UN Clock comparator UN UN Control registers U/V UN General registers U/V UN Floating-point registers U/V U/V Keys in storage U U Volatile main storage U U NonvolatilE! main storage U U TOO Clock U2 U
2 Explanation: S CPU reset is performed. At the completion of this sequence, the CPU is in the stopped state.
N
R U The state of the channel is not affected, and I/O" intelrruption conditions are not cleared, provided the CPU initially is in the stopped state.
When the reset function in the CPU is initiated at the time! the CPU is executing an I/O instruction, is in
the process of taking an I/O interruption, or is
performing the initial-program-Ioading function, the
communication between the CPU and the channel may be terminated, and the resultant state of thl! associated channel, subchannel, and I/O device ill unpredictable. I n this case, an I/O-interruption condition may appear to have been cleared, or an
addiitional I/O-interruption condition may be genElrated. I/O system reset is performed in the configured
channels, and pending I/O-interruption conditions
are 'Cleared. As part of this reset, system reset is
signaled to the I/O control units and devices
con'figured to the channel. The contents, including the checking-block code,
remain unchanged, provided the field is not being
accElssed at the time the reset function is perforrned.
The subsequent contents of a field are unpredictable
if it is accessed at the time of the reset. U/V The' contents remain unchanged, provided the field
is n'ot being accessed at the time the reset function
is performed. However, on some models the checking­ blol:k code of the contents may be made valid. The
subsequent contents' of a field are unpredictable if it
is al:cessed at the ti me of the reset.
Summary of Reset Action
52 Systt!m/370 Principles of Operation ---- S S1 51 5 N
C*
C
C
C I U/V U/V U U U U
2 C
R
R
R
C* 1 C*
1
C*
C
C
C
C
C
C
C
C
C I I I UN C/V C/X U/V C/V C/X U C
C/X
3 U C
C/X3 U C U U
2 U
2 C
3
The contents are cleared to zero with valid checking-block
code.
C/V The checking-block code of the contents is made valid.
The contents normally are cleared to zeros but in some
models may be left unchanged.
C/X The checking-block code of the contents is made valid.
2
3
The contents normally are cleared to zeros but in some
models may be left unpredictable.
The contents are set to their initial values with valid
checking-block code.
Clearing the contents of the P5W to zero causes the CPU to
assume the BC-mode format. The contents of the
instruction-length-code and interruption-code fields remain unpredictab-te, as these values are not retained when a new PSW is introduced.
When the IPL sequence follows the reset function on that CPU, the CPU does not enter the stopped state, and the PSW is not necessarily cleared to zeros.
Access to the TOO clock by means of STOR E CLOCK at
the time a reset function is performed does not cause the
value of the TOO clock to be affected.
When these units are separately powered, the action is
performed only when the power for the unit is turned on.