The ]load key with the enable-system-clear
key in the normal position.
3. When lthe CPU accepts the program-reset or­
der specified by a SIGNAL PROCESSOR in­
struction addressing this CPU. Initial Program Reset
Initial program reset causes initial CPU reset to be
performed and causes I/O system reset to be per­
formed in all channels configured to the CPU. See the table "Summary of Reset Action" for a detailed
description of the effect of the reset on other parts
of the system.
Reset Function CPU Program Initial CPU Initial Program System Clear Power On Area Affected Reset Reset CPU state S S Configured channels N
R PSW U/V U/V Prefix U/V utv CPU timer UN UN Clock comparator UN UN Control registers U/V UN General registers U/V UN Floating-point registers U/V U/V Keys in storage U U Volatile main storage U U NonvolatilE! main storage U U TOO Clock U2 U
2
Explanation: S CPU reset is performed. At the completion of this sequence, the CPU is in the stopped state.
N
R U The state of the channel is not affected, and I/O" intelrruption conditions are not cleared, provided the CPU initially is in the stopped state.
When the reset function in the CPU is initiated at the time! the CPU is executing an I/O instruction, is in
the process of taking an I/O interruption, or is
performing the initial-program-Ioading function, the
communication between the CPU and the channel may be terminated, and the resultant state of thl! associated channel, subchannel, and I/O device ill unpredictable. I n this case, an I/O-interruption condition may appear to have been cleared, or an
addiitional I/O-interruption condition may be genElrated. I/O system reset is performed in the configured
channels, and pending I/O-interruption conditions
are 'Cleared. As part of this reset, system reset is
signaled to the I/O control units and devices
con'figured to the channel. The contents, including the checking-block code,
remain unchanged, provided the field is not being
accElssed at the time the reset function is perforrned.
The subsequent contents of a field are unpredictable
if it is accessed at the time of the reset. U/V The' contents remain unchanged, provided the field
is n'ot being accessed at the time the reset function
is performed. However, on some models the checking­ blol:k code of the contents may be made valid. The
subsequent contents' of a field are unpredictable if it
is al:cessed at the ti me of the reset.
Summary of Reset Action
52 Systt!m/370 Principles of Operation ---- S S1 51 5 N
C*
C
C
C I U/V U/V U U U U
2
C
R
R
R
C* 1 C*
1
C*
C
C
C
C
C
C
C
C
C I I I UN C/V C/X U/V C/V C/X U C
C/X
3 U C
C/X3 U C U U
2
U
2
C
3
The contents are cleared to zero with valid checking-block
code.
C/V The checking-block code of the contents is made valid.
The contents normally are cleared to zeros but in some
models may be left unchanged.
C/X The checking-block code of the contents is made valid.
2
3
The contents normally are cleared to zeros but in some
models may be left unpredictable.
The contents are set to their initial values with valid
checking-block code.
Clearing the contents of the P5W to zero causes the CPU to
assume the BC-mode format. The contents of the
instruction-length-code and interruption-code fields remain unpredictab-te, as these values are not retained when a new PSW is introduced.
When the IPL sequence follows the reset function on that CPU, the CPU does not enter the stopped state, and the PSW is not necessarily cleared to zeros.
Access to the TOO clock by means of STOR E CLOCK at
the time a reset function is performed does not cause the
value of the TOO clock to be affected.
When these units are separately powered, the action is
performed only when the power for the unit is turned on.
Execution of the initial-program-reset function is
initiated in a CPU by one of the following:
1. On a model that does not have the store-status
facility installed, by activating the system-reset
key on that CPU, with the enable-system-clear
key in the normal position.
2. By activating the load key on that CPU, with
the enable-system-clear key in the normal posi­
tion. (The initial-pro gram-reset function is im­
mediately followed by the initial-pro gram­
loading operation.)
3. When the CPU accepts the initial-pro gram­
reset order specified by a SIGNAL PRO­ CESSOR instruction addressing this CPU. System-Clear Reset
System-clear reset causes initial CPU reset to be
performed, causes I/O system reset to be performed
in all channels configured to the CPU, and causes
the contents to be set to zeros with valid checking­
block code in that part of main storage and of keys
in storage that is configured to the CPU. Additional­
ly, the checking-block code of the contents of gener­
al registers and floating-point registers is made valid.
In most models the contents of the registers are
cleared to zeros, but in some the contents may be
left unchanged except for making the checking-block
code valid.
See the table "Summary of Reset Action" for a
detailed description of the effect of the reset on oth­
er parts of the system.
Execution of the system-clear-reset function is
initiated in a CPU by one of the following:
1. By activating the system-reset key on that CPU, with the enable-system-clear key in the
clear position.
2. By activating the load key on that CPU, with
the enable-system-clear key in the clear posi­
tion. (The system-clear function is immediately
followed by the initial-pro gram-loading opera­
tion.)
3. By performing either of the above on any other
configured CPU in a multiprocessing system.
Programming Notes
In order for the CPU-reset and initial-CPU-reset
operations not to affect the contents of fields that
are to be left unchanged, the CPU must not be exe­
cuting instructions and must be disabled for all inter­
ruptions at the time of the reset. Except for the oper­
ation of the interval timer, CPU timer, and clock
comparator and for the possibility of taking a
machine-check interruption, all CPU activity can be
quiesced by placing the CPU in the wait state and by
disabling it for I/O and external interruptions. In
order to avoid the possibility of causing a CPU reset
at the time the timing facilities are being updated or
a machine-check interruption occurs, the CPU must
be in the stopped state.
Resetting of the CPU does not affect the value
and operation of the time-of-day clock.
System-clear reset causes all bit positions of the
interval timer to be cleared to zeros.
The conditions under which the CPU enters the
check-stop state are model-dependent and include
malfunctions that preclude the completion of the
current operation. Hence, in general, when CPU reset or initial CPU reset is executed in a CPU that
is in the check-stop state, the contents of the PSW, addressable registers, and storage locations, includ­
ing the keys, accessed at the time of the error are not
reliable. Power-On Reset
The power-on-reset function for a component of the
system is performed as part of the power-on se­
quence for that component.
The power-on sequences for the TOD clock, main
storage, and channels may be included as part of the CPU power-on sequence, or the power-on sequence
for these units may be initiated separately. The fol­
lowing sections describe the power-on resets for the CPU, TOD clock, and main storage. See also "I/O Operations" and the appropriate Systems Reference
Library (SRL) or System Library (SL) publication
for channels, control units, and I/O devices. CPU Power-On Reset: The power-on reset causes
initial CPU reset to be performed and causes I/O system reset to be performed in all channels config:­ ured to the CPU. The checking-block code on the
contents of general registers and floating-point regis­
ters is made valid. In most models the contents are
cleared to zero, but in some models the contents
may be left unpredictable except for the checking­
block code. TOD Clock Power-On Reset: The power-on reset
causes the value of the time-of -day clock to be set to
zero and causes the clock to enter the not-set state.
Main-Storage Power-On Reset: For volatile main
storage (one that does not preserve its contents
when power is down) and for keys in storage,
power-on reset causes valid checking-block code to
be placed in these fields. In most models the con­
tents are cleared to zeros, but in some models the
contents may be left unpredictable except for the
checking-block code. The contents of nonvolatile System Control 53
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