main storage, including the checking-block code,
remain unchanged.
Store Status
The store-status facility includes the following:
1. Aehange to the operation of the system-reset
key when the enable-system-clear key is in the
normal position. With the store-status facility
installed, pressing the system-reset key causes
a program reset; without this facility, initial
program reset is performed.
2. An operator-initiated store-status function.
The store-status operation consists in placing the
contents of the currentPSW and the program
addressable registers in permanently assigned loca
tions within the first 512 bytes of main storage. In
the BC mode, the instruction-length code in thePSW is unpredictable, and an interruption code of
zero isstored. The information provided for control
register positions not associated with an installed
facilityis unpredictable. If the CPU timer, clock
comparator, prefix register, or floating-point facility
is not installed, the contents of the corresponding
locations in main storage remain unchanged.
The word beginning at absolute storage address
268 is reserved for storing additional status as re
quired by certain model-dependent
feature requiring this field is installed, the contents
of the field remain unchanged upon execution of the
store-status function.
The following table lists the fields that are stored,
their length, and their location in main storage.
Length in Absolute
Field Bytes Address
1CPU timer 8 216
Clock comparator 8 224
CurrentPSW 8 256 Prefix 4 264
Model-dependent feature 4 268F-P registers 0-6 32 352
General registers0-15 64 384
Control registers0-15 64 448
Explanation:
1 DecimaliEiddress of the first byte of the field in absolute main
storage.Permanently Assigned Storage for Store Status
The contents of the registers are not changed. If
an error is encountered during the operation, theCPU enters the check-stop state.
The store-status operation can be initiated by the
operator on the system console. The operator con
trols andl the procedure for initiating the function
may differ among models and are described in theSystem Library (SL) publication for the model. In a
54Sysh:m/370 Principles of Operation
multiprocessing system, the store-status operation
can also be initiated at the addressedCPU by execu
tingSIGNAL PROCESSOR, specifying the stop
and-store-status order.
Initial Program Loading
Initial program loading(IPL) is provided for the
initiation of processing when the contents of main
storage or of the pSW are not suitable for process-
ing.
Initial program loading is initiated manually by
selecting an input device with the load-unit-address
switches and then pressing the load key. Pressing the
load key causes a system-clear or an initial-program
reset operation to be performed on theCPU, as de
termined by the setting of the enable-system-clear
key. Subsequently, a read operation is initiated from
the selected input device.
The read operation is performed as if aSTART I/O instruction were executed that specified the
device addressed by the load-unit-address switches
and used a channel address word ( CAW) containing
a protection key of zero and a channel command
word (CCW) address of0. The address set up on
the load-unit-address switches provides the 12 low
order bits of theI/O address; zeros are implied for
the high-order address bits. Although the location of
the first CCW to be executed is specified as0, the
first CCW actually executed is an implied CCW,
containing, in effect, a read command with the mod
ifier bits set to zero, a data address of0, a byte
count of 24, the chain-command flag on, the
suppress-incorrect-Iength-indication flag on, the
chain-data flag off, the skip flag off, and the
program-controlled-interruption(PCI) flag off. The
CCW fetched, as a result of command chaining,
from location 8 or 16, as well as any subsequent
CCW in theIPL sequence, is interpreted the same as
a CCW in anyI/O operation, with the exception
that thePCI flag is ignored.
When theI/O device provides channel-end status
for the last operation of theIPL chain and no excep
tional conditions are detected in the operation, a
newPSW is obtained from locations 0-7. When this PSW specifies the BC mode, the I/O address that
was used for theIPL operation is stored at locations
2 and 3; when the EC mode is specified, theI/O address is stored at locations 186-187, and zeros are
stored at location 185. The load indicator is turned
off, andCPU operation proceeds under the control
of the newPSW. When channel-end status for the IPL operation is
presented, either separate from or along with device
end status, noI/O interruption condition is generat
ed.Similarly, any PCI flags specified by the pro-
remain unchanged.
Store Status
The store-status facility includes the following:
1. A
key when the enable-system-clear key is in the
normal position. With the store-status facility
installed, pressing the system-reset key causes
a program reset; without this facility, initial
program reset is performed.
2. An operator-initiated store-status function.
The store-status operation consists in placing the
contents of the current
addressable registers in permanently assigned loca
tions within the first 512 bytes of main storage. In
the BC mode, the instruction-length code in the
zero is
register positions not associated with an installed
facility
comparator, prefix register, or floating-point facility
is not installed, the contents of the corresponding
locations in main storage remain unchanged.
The word beginning at absolute storage address
268 is reserved for storing additional status as re
quired by certain model-dependent
feature requiring this field is installed, the contents
of the field remain unchanged upon execution of the
store-status function.
The following table lists the fields that are stored,
their length, and their location in main storage.
Length in Absolute
Field Bytes Address
1
Clock comparator 8 224
Current
Model-dependent feature 4 268
General registers
Control registers
Explanation:
1 Decimal
storage.
The contents of the registers are not changed. If
an error is encountered during the operation, the
The store-status operation can be initiated by the
operator on the system console. The operator con
trols andl the procedure for initiating the function
may differ among models and are described in the
54
multiprocessing system, the store-status operation
can also be initiated at the addressed
ting
and-store-status order.
Initial Program Loading
Initial program loading
initiation of processing when the contents of main
storage or of the pSW are not suitable for process-
ing.
Initial program loading is initiated manually by
selecting an input device with the load-unit-address
switches and then pressing the load key. Pressing the
load key causes a system-clear or an initial-program
reset operation to be performed on the
termined by the setting of the enable-system-clear
key. Subsequently, a read operation is initiated from
the selected input device.
The read operation is performed as if a
device addressed by the load-unit-address switches
and used a channel address word ( CAW) containing
a protection key of zero and a channel command
word (CCW) address of
the load-unit-address switches provides the 12 low
order bits of the
the high-order address bits. Although the location of
the first CCW to be executed is specified as
first CCW actually executed is an implied CCW,
containing, in effect, a read command with the mod
ifier bits set to zero, a data address of
count of 24, the chain-command flag on, the
suppress-incorrect-Iength-indication flag on, the
chain-data flag off, the skip flag off, and the
program-controlled-interruption
CCW fetched, as a result of command chaining,
from location 8 or 16, as well as any subsequent
CCW in the
a CCW in any
that the
When the
for the last operation of the
tional conditions are detected in the operation, a
new
was used for the
2 and 3; when the EC mode is specified, the
stored at location 185. The load indicator is turned
off, and
of the new
presented, either separate from or along with device
end status, no
ed.
