Logical Storage Addressing Control . PSW . Control Register 0 Control Register 1 Translation Tables . Segment-Table Entries Page-Table Entries . TrC)nslation .
Types of Translation Translation Process .
Contents I nspection of Control Register 0 Segment Table Lookup.
Page Table Lookup.
Formation of the Real Address
Addresses Translated Dynamic Address Translation Interlocks Between Logical and Real Storage References
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Translation-Lookaside Buffer . States of Translation-Table Entries
Use of the Translation-Lookaside Buffer .
Modification of Translation Tables Reference and Change Recording.
Address-Translation Exceptions . Summary of Dynamic Address Translation Formats
Dynamic address translation provides the ability to
interrupt the execution of a program at an arbitrary
moment, record it and its data on an external medi­
um, such as a direct-access storage device, and at a
later time return the program and the data to differ­
ent main-storage locations for resumption of execu­
tion. The transfer of the program and its data be­
tween main and external storage may be performed
piecemeal, and the return of the information to main
storage may take place in response to an attempt by
the CPU to access it at the time it is needed for ex­
ecution. These functions may be performed without
change or inspection of the program and its data, do
not require any explicit program!Ring convention for
the relocated program, and do not disturb the execu­
tion of the program except for the time delay in­
volved.
Address translation is achieved by treating the.
addresses supplied by and available to the program
as logical addresses. These logical addresses are
translated by means of translation tables to real
addresses when storage is addressed. The translation
occurs in blocks of addresses, called pages.
With appropriate support by an operating system,
the dynamic-address-translation facility may be used
to provide to a user a system wherein his main stor­
age appears to be larger than the installed main stor-
age. This apparent main storage is referred to as
virtual storage, and the logical addresses used to
designate locations in the virtual storage are referred
to as virtual addresses. The virtual storage of a user
may far exceed the size of the real main storage of
the installation and normally is maintained on an
external storage medium. Only the most recently
referred-to pages of the virtual storage are assigned
to occupy blocks of real main storage. As the user
refers to pages of his virtual storage that do not ap­
pear in real main storage, they are brought in to re­
place pages in real main storage that are less likely to
be needed. The swapping of pages of storage is per­
formed by the operating system without the user's
knowledge.
In the process of replacing blocks of main storage
by new information from an external medium, it
must be determined which block to replace and
whether the block being replaced should be recorded
and preserved on the external medium. To aid in this
decision process, the key in storage is extended with
a reference bit and a change bit.
Dynamic address translation may be specified for
instruction and data addresses generated by the cen­ tral processing unit (CPU), but is not available for
the addressing of data and of control words in I/O operations. To facilitate I/O operations in a virtual-
Dynamic Address Translation 57

storage environment, the indirect-data-addressing
facility is provided in the channel.
The address-translation facility requires that the CPU be equipped with the extended-control facility,
as address translation is under control of bit 5 of the
extended-control (EC) PSW. The address-translation facility includes the in­
structions LOAD REAL ADDRESS, RESET REF­
ERENCE BIT, and PURGE TLB. It makes use of
control register 1 and bits 8-12 in control register O. Logical Storage Addressing
Address translation is achieved by treating the ad­
dresses supplied by the program as logical addresses.
When the dynamic-address-translation facility is
active, a logical address is translated during a storage
reference into the corresponding real address, which
designates a location in real storage. When the
dynamic-address-translation facility is not installed
or translation is not specified, a real address is iden­
tical to the corresponding logical address.
In the process of translation, two types of Units of
information are recognized--segments and pages. A
segment is a block of sequential logical addresses
spanning 65,536 (64K) or 1,048,576 (lM) bytes
and beginning at an address that is a multiple of its
size. The size of the segment is controlled by bits 11
and 12 of control register O. A page is a block of
contiguous storage containing 2,048 (2K) or 4,096
(4K) bytes and beginning at an address that is a
multiple of its size. The size of the page is con­
trolled by bits 8 and 9 of control register O. The logical address, accordingly, is divided into a
segment-index field, a page-index field, and a byte­
index field. The size of these fields depends on the
segment and page size.
The segment index starts with bit 8 of the logical
address and extends through bit 15 for a 64K-·byte segment size and through bit 11 for a 1M-byte seg­
ment size. The page index starts with the bit follow­
ing the segment index and extends through bit 19 for
a 4K-byte page size and through bit 20 for a 2K­
byte page size. The byte index comprises the remain­
ing 11 or 12 low-order bits oJ the logical address.
The formats of the logical address are as follows:
For 64K-byte segments and 4K-byte pages: Segment :----1 __ I_nd_e_x ____ __ -L ____ o 8 16 20 31
58 System/370 Principles of Operation
For 64K-byte segments and 2K-byte pages:
o 8
Segment Index I I Byte Index 16 21
For 1M-byte segments and 4K-byte pages: I Page Index I
Byte Index o 8 12 20 For 1M-byte segments and 2K-byte pages:
31
31 I Page Index I Byte Index I o 8 12 21 31
Logical addresses are translated into real address­
es by means of two translation tables, a segment
table and a page table, which reflect the current as­
signment of real storage. The assignment of real
storage occurs in units of pages, the reallocations being assigned contiguously within a page. The
pages need not be adjacent in real storage even
though assigned to a set of sequential logical address­
es.
Control
Address translation is controlled by the translation­
mode bit in the PSW and by a set of bits in control
registers 0 and 1. Additional controls are located in
the translation tables.
PSW
When the dynamic-address-translation facility is
installed, the CPU can operate either in the transla­
tion mode or without address translation. The mode
of operation is controlled by bit 5 of the extended­
control PSW, the translation-mode bit. When this
bit is one, translation is specified; when this bit is
zero, no implicit dynamic address translation takes
place, and logical addresses are used as real address­
es.
Control Register 0
Four bits are provided in control register 0 for the
control of page size and segment size, as follows:
8 10 12