The bits are defined as follows:
PageSize (PS): Bits 8 and 9 of control register 0 control the size of pages, using the following code:
Bits 8 and 9
ofControl Register 0 01 10 Page Size (Bytes)
2,048 (2K)
4,096 (4K)
When bit positions 8 and 9 contain a binary code
other than01 or 10, a translation-specification ex
ception is recognized as part of the execution of an
instruction using address translation, and the opera
tion is suppressed. These bits are initialized to zeros.
SegmentSize (SS): Bits 11 and 12 of control regis
ter0 control the size of segments, using the follow
ing code:
Bits 11 and 12
ofControl Register 0 00 10 Segment Size (Bytes)
65,536 (64K)
1,048,576 (1M)
When bit position 12 contains a one, a translation
specification exception is recognized as part of the
execution of an instruction using address translation,
and the operation is suppressed. These bits are ini
tialized to zeros.
Bit10 of control register 0 must be zero when an
instruction is executed that uses address translation;
otherwise, a translation-specification exception is
recognized as part of the execution of the instruc
tion, and the operation is suppressed. The bit is not
checked for zero when address translation is not
installed.
Control Register 1
Bits0-25 of control register 1 designate the begin
ning and length of the segment table:
LengthI Segment-Table Addr.ss
o 8 26 31
The fields in the register are allocated as follows:
Segment-Table Length: Bits0-7 of control register 1
designate the length of the segment table in units of
64 bytes, thus making the length of the segment
table variable in multiples of 16 entries. The length
of the segment table, in units of 64 bytes, is equal to
one more than the value in bit positions0-7. The
contents of the length field are used to establish
whether the entry designated by the segment-index
portion of the logical address falls within the seg
ment table.Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Segment-TableAddress: Bits 8-25 of control register 1,
with six low-order zeros appended, form a 24-bit
real address that designates the beginning of the
segment table.
Programming Note
The validity of the information loaded into a control
register, including that pertaining to dynamic address
translation, is not checked at the time the register is
loaded. This information is checked and the pro
gram exception, if any, is indicated at the time the
inf ormation is used.
The information pertaining to dynamic address
translation is considered to be used when an instruc
tion is executed in the translation mode or whenLOAD REAL ADDRESS is executed. The informa
tion is not considered to be used when thePSW specifies translation, but an I/O, external, restart, or
machine-check interruption occurs before an instruc
tion is executed, including the case when thePSW specifies the wait state.
Translation Tables
Two types of translation tables are used for the
translation process-a segment table and a page
table. These tables reside in main storage.
Segment-Table Entries
The entry fetched from the segment table designates
the length, availability, and origin of the correspond
ing page table.
An entry in the segment table has the following
format:Page-Table Address
o 4 8 29 31
The fields in the segment-table entry are allocated
as follows:
Page-Table Length: Bits0-3 designate the length of
the page table in increments that are equal to a six
teenth of the maximum size of the table, the maxi
mum size depending on the size of segments and
pages. The length of the page table, in units one
sixteenth of the maximum size, is equal to one more
than the value in bit positions0-3. The length field is
compared against the high-order four bits of the
page-index portion of the logical address to deter
mine whether the page index designates an entry
within the page table.
Dynamic Address Translation 59
Page
Bits 8 and 9
of
2,048 (2K)
4,096 (4K)
When bit positions 8 and 9 contain a binary code
other than
ception is recognized as part of the execution of an
instruction using address translation, and the opera
tion is suppressed. These bits are initialized to zeros.
Segment
ter
ing code:
Bits 11 and 12
of
65,536 (64K)
1,048,576 (1M)
When bit position 12 contains a one, a translation
specification exception is recognized as part of the
execution of an instruction using address translation,
and the operation is suppressed. These bits are ini
tialized to zeros.
Bit
instruction is executed that uses address translation;
otherwise, a translation-specification exception is
recognized as part of the execution of the instruc
tion, and the operation is suppressed. The bit is not
checked for zero when address translation is not
installed.
Control Register 1
Bits
ning and length of the segment table:
Length
o 8 26 31
The fields in the register are allocated as follows:
Segment-Table Length: Bits
designate the length of the segment table in units of
64 bytes, thus making the length of the segment
table variable in multiples of 16 entries. The length
of the segment table, in units of 64 bytes, is equal to
one more than the value in bit positions
contents of the length field are used to establish
whether the entry designated by the segment-index
portion of the logical address falls within the seg
ment table.
By TNL: GN22-0498
Segment-Table
with six low-order zeros appended, form a 24-bit
real address that designates the beginning of the
segment table.
Programming Note
The validity of the information loaded into a control
register, including that pertaining to dynamic address
translation, is not checked at the time the register is
loaded. This information is checked and the pro
gram exception, if any, is indicated at the time the
inf ormation is used.
The information pertaining to dynamic address
translation is considered to be used when an instruc
tion is executed in the translation mode or when
tion is not considered to be used when the
machine-check interruption occurs before an instruc
tion is executed, including the case when the
Translation Tables
Two types of translation tables are used for the
translation process-a segment table and a page
table. These tables reside in main storage.
Segment-Table Entries
The entry fetched from the segment table designates
the length, availability, and origin of the correspond
ing page table.
An entry in the segment table has the following
format:
o 4 8 29 31
The fields in the segment-table entry are allocated
as follows:
Page-Table Length: Bits
the page table in increments that are equal to a six
teenth of the maximum size of the table, the maxi
mum size depending on the size of segments and
pages. The length of the page table, in units one
sixteenth of the maximum size, is equal to one more
than the value in bit positions
compared against the high-order four bits of the
page-index portion of the logical address to deter
mine whether the page index designates an entry
within the page table.
Dynamic Address Translation 59