The bits are defined as follows:
Page Size (PS): Bits 8 and 9 of control register 0 control the size of pages, using the following code:
Bits 8 and 9
of Control Register 0 01 10 Page Size (Bytes)
2,048 (2K)
4,096 (4K)
When bit positions 8 and 9 contain a binary code
other than 01 or 10, a translation-specification ex­
ception is recognized as part of the execution of an
instruction using address translation, and the opera­
tion is suppressed. These bits are initialized to zeros.
Segment Size (SS): Bits 11 and 12 of control regis­
ter 0 control the size of segments, using the follow­
ing code:
Bits 11 and 12
of Control Register 0 00 10 Segment Size (Bytes)
65,536 (64K)
1,048,576 (1M)
When bit position 12 contains a one, a translation­
specification exception is recognized as part of the
execution of an instruction using address translation,
and the operation is suppressed. These bits are ini­
tialized to zeros.
Bit 10 of control register 0 must be zero when an
instruction is executed that uses address translation;
otherwise, a translation-specification exception is
recognized as part of the execution of the instruc­
tion, and the operation is suppressed. The bit is not
checked for zero when address translation is not
installed.
Control Register 1
Bits 0-25 of control register 1 designate the begin­
ning and length of the segment table:
Length I Segment-Table Addr.ss
o 8 26 31
The fields in the register are allocated as follows:
Segment-Table Length: Bits 0-7 of control register 1
designate the length of the segment table in units of
64 bytes, thus making the length of the segment
table variable in multiples of 16 entries. The length
of the segment table, in units of 64 bytes, is equal to
one more than the value in bit positions 0-7. The
contents of the length field are used to establish
whether the entry designated by the segment-index
portion of the logical address falls within the seg­
ment table. Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Segment-Table Address: Bits 8-25 of control register 1,
with six low-order zeros appended, form a 24-bit
real address that designates the beginning of the
segment table.
Programming Note
The validity of the information loaded into a control
register, including that pertaining to dynamic address
translation, is not checked at the time the register is
loaded. This information is checked and the pro­
gram exception, if any, is indicated at the time the
inf ormation is used.
The information pertaining to dynamic address
translation is considered to be used when an instruc­
tion is executed in the translation mode or when LOAD REAL ADDRESS is executed. The informa­
tion is not considered to be used when the PSW specifies translation, but an I/O, external, restart, or
machine-check interruption occurs before an instruc­
tion is executed, including the case when the PSW specifies the wait state.
Translation Tables
Two types of translation tables are used for the
translation process-a segment table and a page
table. These tables reside in main storage.
Segment-Table Entries
The entry fetched from the segment table designates
the length, availability, and origin of the correspond­
ing page table.
An entry in the segment table has the following
format: Page-Table Address
o 4 8 29 31
The fields in the segment-table entry are allocated
as follows:
Page-Table Length: Bits 0-3 designate the length of
the page table in increments that are equal to a six­
teenth of the maximum size of the table, the maxi­
mum size depending on the size of segments and
pages. The length of the page table, in units one­
sixteenth of the maximum size, is equal to one more
than the value in bit positions 0-3. The length field is
compared against the high-order four bits of the
page-index portion of the logical address to deter­
mine whether the page index designates an entry
within the page table.
Dynamic Address Translation 59
Page-Table Address: Bits 8-28, with three low-order
zeros :appended, form a 24-bit real address that des­
ignates the beginning of the page table. Bit: Bit 31 controls whether the
segment associated with the segment-table entry is
available. When bit position 31 contains a zero, ad­
dress translation proceeds using the designated page
table. When the bit is a one, a segment-translation
exception is recognized, and the unit of operation is nullified. The handling of bit positions 4-7 and 29-30 of
the segment-table entry depends on the model. Nor­
mally a translation-specification exception is recog­
nized and the unit of operation is suppressed when
these bits are not zeros; however, on some models
the contents of these bit positions may be ignored. Table Entries
The entry fetched from the page table indicates the
availability of the page and contains the high-order
bits of the real address. The format of the page-table
entry depends on page size, as follows: Page-table entry with 4K-byte pages: Add,." o Page··table entry with 2K-byte pages: L Page Add,." o
The fields in the page-table entry are allocated as
follows:
Page Address: Bits 0-11 or bits 0-12, depending on
the page size, provide the leftmost 12 or 13 bits of a
24-bit real storage address. When the page address
and the contents of the byte-index field of the logi­
cal address are concatenated, with the page address
forming the high-order part, the real storage address
is obtained.
Page'-Invalid Bit: Bit 12 or 13, depending on the
page size, controls whether the page associated with
the page-table entry is available. When the bit is
zero" address translation proceeds using the table
entry. When the bit is one, a page-translation excep­
tion is recognized, and the unit of operation is nulli­
fied.
Except for the rightmost bit position of the entry,
the bit positions to the right of the page-invalid bit
must contain zeros; otherwise, a translation- 60 System/370 Principles of Operation
specification exception is recognized as part of the
execution of an instruction using that entry for ad­
dress translation, and the unit of operation is sup­
pressed.
Programming Notes
A segment-table or page-table length code in excess
of the maximum usable length code is valid. For
example, the length code is valid even if the end of
the table falls outside the available main storage or if
part of the table is not addressable by the logical
address.
The low-order bit position of a page-table entry is
unassigned and is not checked for zero; thus, it is
available for programming use.
Translation
Types of Translation
Two types of translation of main-storage addresses
are distinguished--implicit and explicit. An explicit
translation is one that is invoked for the translation
of the operand address of LOAD REAL ADDRESS. The procedure invoked for the translation of all in­
struction addresses and of addresses of main-storage
operands for all other instructions is referred to as
implicit translation.
Translation Process
Translation is performed by means of a segment
table and a page table, both of which reside in main
storage. It is controlled by the translation-mode bit
in the PSW and by a set of bits in control registers 0 and 1.
The segment-index portion of the logical address
is used to select an entry from the segment table, the
starting address and length of which are specified by
the contents of control register 1. This entry desig­
nates the page table to be used. The page-index por­
tion of the logical address is used to select an entry
from the page table. This entry, the format of which
depends on the size of the page, contains the high­
order bits of the real address that corresponds to the
logical address. The byte-index field of the logical
address is used unchanged for the low-order bit posi­
tions of the real address.
In order to avoid the delay associated with refer­
ences to translation tables in main storage, the in­
formation fetched from the tables normally is placed
also in a special buffer, the translation-lookaside
buffer (TLB), and subsequent translations involving
the same table entries may be performed using the
information recorded in the TLB.
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