dress is obtained by appending three low-order zeros
to the contents of bit positions 8-28 of the segment­
table entry and adding the page index to this value.
The addition is performed with the low-order bit of
the page-index aligned with bit 30 of the page-table
address.
As part of the page-table lookup process, the four
high-order bits of the page index are compared
against the page-table length, bits 0-3 of the
segment-table entry, to establish whether the ad­
dressed entry is within the table. If the value in the
page-table-length field is less than the value in the
four high-order bit positions of the page-index field,
a page-translation exception is recognized, and the
unit of is nullified.
If the storage address generated for fetching the
page-table entry refers to a location outside the main
storage of the installed system, an addressing excep­
tion is recognized, and the unit of operation is sup­
pressed.
The entry fetched from the page table indicates
the availability of the page and contains the high­
order bits of the real address. The page-invalid bit is
inspected to establish whether the corresponding
page is available. If this bit is one, a page-translation
exception is recognized, and the unit of operation is
nullified. If bit positions 13-14 for 4K-byte pages or
bit position 14 for 2K-byte pages contains one, a
translation-specification exception is recognized, and
the unit of operation is suppressed.
Formation of the Real Address
When no exceptions in the translation process are
encountered, the real page address obtained from
the page-table entry and the byte-index portion of
the logical address are concatenated, with the page
address forming the high-order part. The result
forms the real storage address.
Whenever access to main storage is made during
the address translation process for the purpose of
fetching an entry from a segment or page table, stor­
age protection is ignored; that is, the reference is
made as if the storage location containing the
translation-table entry were 110t protected against
fetching.
Programming Note
When more than one exception is encountered in the
process of address translation, only the exception
with the highest priority is indicated with the pro­
gram interruption. The priority in which exceptions
are recognized is listed in the table "Priorities of .
Access Exeeptions" in the chapter "Interruptions." 62 System/370 Principles of Operation
Addresses Translated
All main storage addresses that are explicitly speci­
fied by the program and are used by the CPU to
refer to main storage for an instruction or an oper­
and are logical addresses and are subject to dynamic
address translation. Analogously, the corresponding
addresses indicated to the program on an interrup­
tion or as the result of executing an instruction are
logical, as are the addresses in control registers 10 and 11 designating the starting and ending locations
for program-event recording (PER). Translation is not applied to addresses explicitly
designating keys in storage (operand addresses in
SET STORAGE KEY, INSERT STORAGE KEY,
and RESET REFERENCE BIT) and to quantities
that are formed as storage addresses from the values
designated in the Band D fields of an instruction but
that are not used to address main storage. The latter
include operand addresses in LOAD ADDRESS,
MONITOR CALL, and the shifting and 110 in­
structions. Similarly, translation is not applied to the
addresses implicitly used by the CPU or channel for
such sequences as interruptions, updating the inter­
val timer at location 80, address translation, and
logout, including the machine-check-extended­
logout address in control register 15. However, when
the program explicitly designates these locations as
the source of an operand or instruction, the address­
es are subject to translation.
Dynamic address translation is not applied to the
addresses used by channels to transfer data, channel­
command words, or indirect-data-address words.
Similarly, dynamic address translation is not applied
to the I/O-extended-Iogout address at location 172.
The handling of storage addresses associated with
DIAGNOSE is model-dependent.
The processing of addresses, including dynamic
address translation and prefixing, is summarized in
the charts "Types of Addresses" and "Handling of Absolute, real, and logical addresses are distinguished on the
basis of the transformations that are applied to the address
during a storage access.
An absolute address is the address assigned to a main-storage location. An absolute address is used for a storage access
without any transformations performed on it.
A real address identifies a location in real main storage. When
a real address is used for an access to main storage, it is
converted, by means of prefixing, to an absolute address.
When a logical address is used for an access to main storage,
it is translated, by means of dynamic address translation, to
a real address and subsequently is converted, by means of
prefixing, to an absolute address.
Types of Addresses

Addresses." Prefixing, when provided, is applied
after the address has been translated by means of
the dynamic-address-translation facility. For a de­
scription of prefixing, see "Prefixing" in the chapter
"Multiprocessing. " Interlocks Between Logical and Real
Storage References
When dynamic address translation is not invoked,
the results stored by one instruction appear to that CPU to be completed before execution of the next
instruction, including the instruction fetch, is begun.
When an instruction has two main-storage operands,
the handling of overlapped main-storage operands is
included as part of the instruction definition.
When dynamic address translation is invoked and
translation tables are constructed such that a loca­
tion in real storage is designated by one and only
one logical address, overlapping operands and
changes to subsequent instructions are handled in
the same way as when the references are made by
real addresses.
With dynamic address translation, a location in
real main storage may have multiple logical address­
es. That is, the translation tables may be set up in
such a way that more than one logical page address
(segment-index and page-index portion of logical
address) is translated to the same real page address. Only when the tables are set up in this way and
Logical Addresses Explicitly Designated by the Program: • I nstruction address in PSW • Branch addresses • Addresses of operands in main storage • Operand address in LOAD REAL ADDRESS • PER starting address in control register 10 and PER ending
address in control register 11
Real Addresses Explicitly Designated by the Program: • Operand addresses in SET STORAGE KEY, INSERT STORAGE KEY, and RESET REFERENCE BIT • MCEL address in control register 15 • Segment-table address in control register 1 • Page-table address in segment-table entry • Page address in page-table entry
Absolute Addresses Explicitly Designated by the Program: • Prefix value • CCW address in CAW • Data address in CCW • CCW address in a CCW specifying transfer in channel • Data address in indirect-data-address words • 10EL address at reallocation 172
Addresses Not Used to Address Storage: • Operand addresses specifying the amount of shift in the
shift insrtuctions • Operand address in LOAD ADDRESS • Operand address in MONITOR CALL • Second-operand address in SIGNAL PROCESSOR • I/O addresses in I/O instructions
Handling of Addresses
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
when more than one logical page address is used to
refer to a reallocation as a source of an instruction or
operand, the following exceptions to the normal inter­
locks occur:
1. When an instruction changes the contents of a
storage location from which a subsequent in­
struction has been prefetched and when differ­
ent logical page addresses are used to designate
that location for storing the result and fetching
the instruction, the use of the common real
location is not necessarily recognized. An in­
struction may be prefetched using a translated
logical address only when the associated
dynamic-address-translation table entries are
attached and valid. Instructions which are pre­
fetched may be interpreted for execution only
for the same logical address for which the in­
struction was prefetched. All copies of pre­
fetched instructions are discarded when the CPU enters or leaves translation mode, when
changes are made to the translation parameters
in control registers 0 and 1 while the CPU is in
the translation mode, when a serializing op­
eration is performed, and when the CPU enters
the operating state.
2. When both operands in a unit of operation
include the same real storage location (the oper­
ands overlap in real storage) and the common
location is designated in the two operands by
Real Addresses Used Implicitly: • Addresses of PSWs used during interruption • Address used by CPU to update interval timer at real
location 80 • Address of CAW, CSW, and other locations used during an I/O interruption or during execution of an I/O instruction.
including STORE CHANNEL ID Absolute Addresses Used Implicitly: • Addresses used for the store-status function
Logical Addresses Provided to the Program: • Address stored in instruction-address field of old PSW on
interruption • Address stored by BRANCH AND LINK • Address stored in register 1 by TRANSLATE AND TEST and EDIT AND MARK • Address stored at real location 144 on a program interrup­
tion for page-translation or segment-translation exception • Address stored at real location 152 on a program interrup­
tion for PER
Real Addresses Provided to the Program: • The translated address generated by LOAD REAL ADDRESS • Address of segment-table entry or page-table entry provided
by LOAD REAL ADDRESS Absolute Addresses Provided to the Program: • Failing-storage address at real location 248 • CCW address in CSW Dynamic Address Translation 63