Addresses." Prefixing, when provided, is applied
after the address has been translated by means of
the dynamic-address-translation facility. For a de
scription of prefixing, see"Prefixing" in the chapter
"Multiprocessing." Interlocks Between Logical and Real
Storage References
When dynamic address translation is not invoked,
the results stored by one instruction appear to thatCPU to be completed before execution of the next
instruction, including the instruction fetch, is begun.
When an instruction has two main-storage operands,
the handling of overlapped main-storage operands is
included as part of the instruction definition.
When dynamic address translation is invoked and
translation tables are constructed such that a loca
tion in real storage is designated by one and only
one logical address, overlapping operands and
changes to subsequent instructions are handled in
the same way as when the references are made by
real addresses.
With dynamic address translation, a location in
real main storage may have multiple logical address
es. That is, the translation tables may be set up in
such a way that more than one logical page address
(segment-index and page-index portion of logical
address) is translated to the same real page address.Only when the tables are set up in this way and
Logical Addresses Explicitly Designated by the Program:• I nstruction address in PSW • Branch addresses • Addresses of operands in main storage • Operand address in LOAD REAL ADDRESS • PER starting address in control register 10 and PER ending
address in control register 11
Real Addresses Explicitly Designated by the Program:• Operand addresses in SET STORAGE KEY, INSERT STORAGE KEY, and RESET REFERENCE BIT • MCEL address in control register 15 • Segment-table address in control register 1 • Page-table address in segment-table entry • Page address in page-table entry
Absolute Addresses Explicitly Designated by the Program:• Prefix value • CCW address in CAW • Data address in CCW • CCW address in a CCW specifying transfer in channel • Data address in indirect-data-address words • 10EL address at reallocation 172
Addresses Not Used to Address Storage:• Operand addresses specifying the amount of shift in the
shift insrtuctions• Operand address in LOAD ADDRESS • Operand address in MONITOR CALL • Second-operand address in SIGNAL PROCESSOR • I/O addresses in I/O instructions
Handling of Addresses
Page ofGA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
when more than one logical page address is used to
refer to a reallocation as a source of an instruction or
operand, the following exceptions to the normal inter
locks occur:
1. When an instruction changes the contents of a
storage location from which a subsequent in
struction has been prefetched and when differ
ent logical page addresses are used to designate
that location for storing the result and fetching
the instruction, the use of the common real
location is not necessarily recognized. An in
struction may be prefetched using a translated
logical address only when the associated
dynamic-address-translation table entries are
attached and valid. Instructions which are pre
fetched may be interpreted for execution only
for the same logical address for which the in
struction was prefetched. All copies of pre
fetched instructions are discarded when theCPU enters or leaves translation mode, when
changes are made to the translation parameters
in control registers0 and 1 while the CPU is in
the translation mode, when a serializing op
eration is performed, and when theCPU enters
the operating state.
2. When both operands in a unit of operation
include the same real storage location (the oper
ands overlap in real storage) and the common
location is designated in the two operands by
Real Addresses Used Implicitly:• Addresses of PSWs used during interruption • Address used by CPU to update interval timer at real
location80 • Address of CAW, CSW, and other locations used during an I/O interruption or during execution of an I/O instruction.
includingSTORE CHANNEL ID Absolute Addresses Used Implicitly: • Addresses used for the store-status function
Logical Addresses Provided to the Program:• Address stored in instruction-address field of old PSW on
interruption• Address stored by BRANCH AND LINK • Address stored in register 1 by TRANSLATE AND TEST and EDIT AND MARK • Address stored at real location 144 on a program interrup
tion for page-translation or segment-translation exception• Address stored at real location 152 on a program interrup
tion for PER
Real Addresses Provided to the Program:• The translated address generated by LOAD REAL ADDRESS • Address of segment-table entry or page-table entry provided
byLOAD REAL ADDRESS Absolute Addresses Provided to the Program: • Failing-storage address at real location 248 • CCW address in CSW Dynamic Address Translation 63
after the address has been translated by means of
the dynamic-address-translation facility. For a de
scription of prefixing, see
"Multiprocessing.
Storage References
When dynamic address translation is not invoked,
the results stored by one instruction appear to that
instruction, including the instruction fetch, is begun.
When an instruction has two main-storage operands,
the handling of overlapped main-storage operands is
included as part of the instruction definition.
When dynamic address translation is invoked and
translation tables are constructed such that a loca
tion in real storage is designated by one and only
one logical address, overlapping operands and
changes to subsequent instructions are handled in
the same way as when the references are made by
real addresses.
With dynamic address translation, a location in
real main storage may have multiple logical address
es. That is, the translation tables may be set up in
such a way that more than one logical page address
(segment-index and page-index portion of logical
address) is translated to the same real page address.
Logical Addresses Explicitly Designated by the Program:
address in control register 11
Real Addresses Explicitly Designated by the Program:
Absolute Addresses Explicitly Designated by the Program:
Addresses Not Used to Address Storage:
shift insrtuctions
Handling of Addresses
Page of
By TNL: GN22-0498
when more than one logical page address is used to
refer to a reallocation as a source of an instruction or
operand, the following exceptions to the normal inter
locks occur:
1. When an instruction changes the contents of a
storage location from which a subsequent in
struction has been prefetched and when differ
ent logical page addresses are used to designate
that location for storing the result and fetching
the instruction, the use of the common real
location is not necessarily recognized. An in
struction may be prefetched using a translated
logical address only when the associated
dynamic-address-translation table entries are
attached and valid. Instructions which are pre
fetched may be interpreted for execution only
for the same logical address for which the in
struction was prefetched. All copies of pre
fetched instructions are discarded when the
changes are made to the translation parameters
in control registers
the translation mode, when a serializing op
eration is performed, and when the
the operating state.
2. When both operands in a unit of operation
include the same real storage location (the oper
ands overlap in real storage) and the common
location is designated in the two operands by
Real Addresses Used Implicitly:
location
including
Logical Addresses Provided to the Program:
interruption
tion for page-translation or segment-translation exception
tion for PER
Real Addresses Provided to the Program:
by