Addresses." Prefixing, when provided, is applied
after the address has been translated by means of
the dynamic-address-translation facility. For a de­
scription of prefixing, see "Prefixing" in the chapter
"Multiprocessing. " Interlocks Between Logical and Real
Storage References
When dynamic address translation is not invoked,
the results stored by one instruction appear to that CPU to be completed before execution of the next
instruction, including the instruction fetch, is begun.
When an instruction has two main-storage operands,
the handling of overlapped main-storage operands is
included as part of the instruction definition.
When dynamic address translation is invoked and
translation tables are constructed such that a loca­
tion in real storage is designated by one and only
one logical address, overlapping operands and
changes to subsequent instructions are handled in
the same way as when the references are made by
real addresses.
With dynamic address translation, a location in
real main storage may have multiple logical address­
es. That is, the translation tables may be set up in
such a way that more than one logical page address
(segment-index and page-index portion of logical
address) is translated to the same real page address. Only when the tables are set up in this way and
Logical Addresses Explicitly Designated by the Program: I nstruction address in PSW Branch addresses Addresses of operands in main storage Operand address in LOAD REAL ADDRESS PER starting address in control register 10 and PER ending
address in control register 11
Real Addresses Explicitly Designated by the Program: Operand addresses in SET STORAGE KEY, INSERT STORAGE KEY, and RESET REFERENCE BIT MCEL address in control register 15 Segment-table address in control register 1 Page-table address in segment-table entry Page address in page-table entry
Absolute Addresses Explicitly Designated by the Program: Prefix value CCW address in CAW Data address in CCW CCW address in a CCW specifying transfer in channel Data address in indirect-data-address words 10EL address at reallocation 172
Addresses Not Used to Address Storage: Operand addresses specifying the amount of shift in the
shift insrtuctions Operand address in LOAD ADDRESS Operand address in MONITOR CALL Second-operand address in SIGNAL PROCESSOR I/O addresses in I/O instructions
Handling of Addresses
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
when more than one logical page address is used to
refer to a reallocation as a source of an instruction or
operand, the following exceptions to the normal inter­
locks occur:
1. When an instruction changes the contents of a
storage location from which a subsequent in­
struction has been prefetched and when differ­
ent logical page addresses are used to designate
that location for storing the result and fetching
the instruction, the use of the common real
location is not necessarily recognized. An in­
struction may be prefetched using a translated
logical address only when the associated
dynamic-address-translation table entries are
attached and valid. Instructions which are pre­
fetched may be interpreted for execution only
for the same logical address for which the in­
struction was prefetched. All copies of pre­
fetched instructions are discarded when the CPU enters or leaves translation mode, when
changes are made to the translation parameters
in control registers 0 and 1 while the CPU is in
the translation mode, when a serializing op­
eration is performed, and when the CPU enters
the operating state.
2. When both operands in a unit of operation
include the same real storage location (the oper­
ands overlap in real storage) and the common
location is designated in the two operands by
Real Addresses Used Implicitly: Addresses of PSWs used during interruption Address used by CPU to update interval timer at real
location 80 Address of CAW, CSW, and other locations used during an I/O interruption or during execution of an I/O instruction.
including STORE CHANNEL ID Absolute Addresses Used Implicitly: Addresses used for the store-status function
Logical Addresses Provided to the Program: Address stored in instruction-address field of old PSW on
interruption Address stored by BRANCH AND LINK Address stored in register 1 by TRANSLATE AND TEST and EDIT AND MARK Address stored at real location 144 on a program interrup­
tion for page-translation or segment-translation exception Address stored at real location 152 on a program interrup­
tion for PER
Real Addresses Provided to the Program: The translated address generated by LOAD REAL ADDRESS Address of segment-table entry or page-table entry provided
by LOAD REAL ADDRESS Absolute Addresses Provided to the Program: Failing-storage address at real location 248 CCW address in CSW Dynamic Address Translation 63
Page of GA22-70004 Revised September 1, 1975
By TNL: GN22-0498
different logical page the use of the Gommon reallocation is not necessarily recog­
nized.
When the use of a common real storage location
is not recognized, storing into the location does not
necess.arily appear to be completed by the time the instruetion or operand is fetched from the location.
In the case of unrecognized operand overlap, the
portion of the instruction definition pertaining to
overlap does not necessarily apply.
Any change to the key in storage appears to be
completed before the following reference to the as­
sociated storage block is made, regardless of whether
the reference to the storage location is made by a
logical or real address. Analogously, any prior refer­
ences to the storage block appear completed when
the key for that block is changed or inspected. Sinee the interlocks discussed in this section peI:­ tain to references made by the same CPU, a com­
mon reallocation implies also a common absolute
location. This is true because, for anyone CPU, a
one-to-one correspondence exists between real and
absolute addresses, and a change in the prefix value,
changing this mapping, causes serialization. interlocks between storage referenees are
summarized in the table "Summary of Interlocks
Between Storage References."
Table Manipulation
Translation-Lookaside Buffer
To enhance performance, the dynamic-address­
translation mechanism normally is implemented such
that some of the information specified in the seg-
ment and page tables is maintained in a special buff­
er, referred to as the translation-Iookaside buffer
(TLB). The CPU necessarily refers to a table entry
in main storage only for the initial access to that
entry. This information subsequently may be main­
tained in the TLB, and all subsequent translations
involving translation-table entries from the same real
storage location may be performed using the info:r­
mation recorded in the TLB. The presence of the TLB
affects the translation process to the extent that a
modification of the contents of a table entry in main
storage does not necessarily have an immediate ef­
fect' if any, on the translation.
The size and the structure of the TLB depends on
the model. For instance, the TLB may be imple­
mented such as to contain only a few entries pertain­
ing to the currently designated segment table, each
entry consisting of the high-order portions of a logi­
cal address and its corresponding real address; or it
may contain arrays of values where the real page
address is selected on the basis of the current
segment-table starting address, page-size designa­
tion, segment-size designation, and the high-order
bits of the logical address. Entries within the TLB
are not explicitly addressable by the program.
The following sections describe the conditions
under which information may be placed in the TLB
and information from the TLB may be used for ad­
dress translation, and describe how changes to the
translation tables affect the translation process. In­
formation is not necessarily retained ih the TLB
under all conditions for which such retention is per­
missible. Furthermore, information in the TLB may I nterlolcks between two references by a single CPU to a location in real storage when the same real location is designated by different addresses. Is it necessarily recognized that reference is made to the same real location? Addresses used to designate a location in real storage Real X and Real X Real X and Logical A Logical A and Logical A Logical A and Logical B Explanation: Not applicable. References within
Same Instruction Operand-Operand
Yes
Yes
No
References by Two Instructions Operand-Operand Operand-I nstruction
Yes Yes
Yes Yes
Yes Yes
Yes No*
* Real X Logical A Logical B
Reference to the same real location is recognized when a serialization function occurs between the two references.
A real address designating location X in real storage.
A logical address A designating location X in real storage.
A logical address B deSignating location X in real storage. Summary of Interlocks Between Storage References
64 System/370 Principles of Operation
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