Control Register 1 Logical Address I I I I Segment Page I Byte Index J Ingex Ini ex - .-l J L CD I CD Segment Table * + + , Page Table*
( ) I CD ® J. CD __ 0 I ". .- -l CD @ l L..o..- I I Translation- Lookaside
Buffer (TLB) Real Address
* In Main Storage CD Information, which may include portions of the logical address and the segment·table address,
is used to search the TLB. ® If match exists, address from TLB is used in forming the real address. 0) If no match exists, table entries in main storage are fetched to translate the address. Resulting value, in conjunction with search information, is used to form an entry in the TLB.
Translation Process The translation process, including the effect of
the TLB, is shown graphically in the figure "Translation Process." Inspection of Control Register 0
The interpretation of the logical address for transla­
tion purposes is controlled by the segment size and
page size, which are specified by the contents of bit
positions 8-12 of control register O. If bit positions
8-9 or 11-12 contain an invalid code or if bit 10 is
one, a translation-specification exception is recog­
nized, and the operation is suppressed.
Segment Table Lookup
The segment-index portion of the logical address is
used to select a segment-table entry that designates
the page table to be used in arriving at the real ad­
dress. The address of the segment-table entry is ob­
tained by appending six low-order zeros to the con­
tents of bit positions 8-25 of control register 1 and
adding the segment index to this value, with the low­
order bit position of the segment index aligned with
bit position 29 of the segment-table address.
As part of the segment-table lookup process, the
segment index is compared against the segment-table
length, bits 0-7 of control register 1, to establish
whether the addressed entry is within the table.
With 1M-byte segments, entries for all addressable
segments are contained in a table of minimum length
(length code of 0). With 64K-byte segments, four
high-order zeros are appended to the contents of bit
positions 8-11 of the logical address, and this ex­
tended value is compared against the eight-bit
segment-table length. If the value in the segment­
table-length field is less than the value in the corre­
sponding bit positions of the logical address, a
segment-translation exception is recognized, and the
unit of operation is nullified.
If the storage address generated for fetching the
segment-table entry refers to a location outside the
main storage of the installed system, an addressing
exception is recognized, and the unit of operation is
suppressed.
Bit 31 of the entry fetched from the segment ta­
ble specifies whether the corresponding segment is
available. This bit is inspected, and, if it is one, a
segment-translation exception is recognized, with the
unit of operation nullified. Handling of bit positions
4-7 and 29-30 of the segment-table entry depends
on the model: normally a translation-specification
exception is indicated and the unit of operation is
suppressed when they do not contain zeros; howev­
er, on some models they may be ignored.
When no exceptions are recognized in the process
of segment-table lookup, the entry fetched from the
segment table designates the length and beginning of
the corresponding page table.
Page Table Lookup
The page-index portion of the logical address, in
conjunction with the page-table address derived
from the segment-table entry, is used to select an
entry from the page table. The page-table-entry ad-
Dynamic Address Translation 61
dress is obtained by appending three low-order zeros
to the contents of bit positions 8-28 of the segment­
table entry and adding the page index to this value.
The addition is performed with the low-order bit of
the page-index aligned with bit 30 of the page-table
address.
As part of the page-table lookup process, the four
high-order bits of the page index are compared
against the page-table length, bits 0-3 of the
segment-table entry, to establish whether the ad­
dressed entry is within the table. If the value in the
page-table-length field is less than the value in the
four high-order bit positions of the page-index field,
a page-translation exception is recognized, and the
unit of is nullified.
If the storage address generated for fetching the
page-table entry refers to a location outside the main
storage of the installed system, an addressing excep­
tion is recognized, and the unit of operation is sup­
pressed.
The entry fetched from the page table indicates
the availability of the page and contains the high­
order bits of the real address. The page-invalid bit is
inspected to establish whether the corresponding
page is available. If this bit is one, a page-translation
exception is recognized, and the unit of operation is
nullified. If bit positions 13-14 for 4K-byte pages or
bit position 14 for 2K-byte pages contains one, a
translation-specification exception is recognized, and
the unit of operation is suppressed.
Formation of the Real Address
When no exceptions in the translation process are
encountered, the real page address obtained from
the page-table entry and the byte-index portion of
the logical address are concatenated, with the page
address forming the high-order part. The result
forms the real storage address.
Whenever access to main storage is made during
the address translation process for the purpose of
fetching an entry from a segment or page table, stor­
age protection is ignored; that is, the reference is
made as if the storage location containing the
translation-table entry were 110t protected against
fetching.
Programming Note
When more than one exception is encountered in the
process of address translation, only the exception
with the highest priority is indicated with the pro­
gram interruption. The priority in which exceptions
are recognized is listed in the table "Priorities of .
Access Exeeptions" in the chapter "Interruptions." 62 System/370 Principles of Operation
Addresses Translated
All main storage addresses that are explicitly speci­
fied by the program and are used by the CPU to
refer to main storage for an instruction or an oper­
and are logical addresses and are subject to dynamic
address translation. Analogously, the corresponding
addresses indicated to the program on an interrup­
tion or as the result of executing an instruction are
logical, as are the addresses in control registers 10 and 11 designating the starting and ending locations
for program-event recording (PER). Translation is not applied to addresses explicitly
designating keys in storage (operand addresses in
SET STORAGE KEY, INSERT STORAGE KEY,
and RESET REFERENCE BIT) and to quantities
that are formed as storage addresses from the values
designated in the Band D fields of an instruction but
that are not used to address main storage. The latter
include operand addresses in LOAD ADDRESS,
MONITOR CALL, and the shifting and 110 in­
structions. Similarly, translation is not applied to the
addresses implicitly used by the CPU or channel for
such sequences as interruptions, updating the inter­
val timer at location 80, address translation, and
logout, including the machine-check-extended­
logout address in control register 15. However, when
the program explicitly designates these locations as
the source of an operand or instruction, the address­
es are subject to translation.
Dynamic address translation is not applied to the
addresses used by channels to transfer data, channel­
command words, or indirect-data-address words.
Similarly, dynamic address translation is not applied
to the I/O-extended-Iogout address at location 172.
The handling of storage addresses associated with
DIAGNOSE is model-dependent.
The processing of addresses, including dynamic
address translation and prefixing, is summarized in
the charts "Types of Addresses" and "Handling of Absolute, real, and logical addresses are distinguished on the
basis of the transformations that are applied to the address
during a storage access.
An absolute address is the address assigned to a main-storage location. An absolute address is used for a storage access
without any transformations performed on it.
A real address identifies a location in real main storage. When
a real address is used for an access to main storage, it is
converted, by means of prefixing, to an absolute address.
When a logical address is used for an access to main storage,
it is translated, by means of dynamic address translation, to
a real address and subsequently is converted, by means of
prefixing, to an absolute address.
Types of Addresses
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