Page ofGA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
tion as part of the execution of the current instruc­
tion, and such loading can occur when the wait state
is spedfied. Similarly, information from a segment­
table or page-table entry having a format error may
be re(!orded in the TLB.
More than one copy of a table entry may exist in
the TLB. For example, some implementations may
cause a copy of a valid table entry to be placed in
the TLB for each segment-table address by which
the entry becomes attached, and some implementa­
tions may cause a valid page-table entry to be placed
in the TLB for each attached and valid segment­
table entry by which the page-table entry is desig­
nated.
Modification of Translation Tables
When an inactive, attached, and invalid table entry is
made valid, the change takes effect immediately.
Similarly, when an inactive, unattached, and valid
page-table entry is made attached by making an
inactive, attached, and invalid segment-table entry
valid, the change takes effect immediately.
However, since the exceptions associated with
dynamic address translation may be established by a
pretest for operand accessibility that is performed as
part of the initiation of the execution of the instruc­
tion, :a segment-translation or 'page-translation ex­
ception may be indicated on the basis of the state of
the table entry at the start of the execution of an
instruction. Consequently, a segment-translation or
page-translation exception may be indicated when a
table entry is invalid at the start of execution even if
the instruction would have validated the table entry
it uses and the table entry would have appeared valid
if the instruction were considered to process the
operands one byte at a time. See the section
"Recognition of Access Exceptions" in the chapter
"Interruptions" for the recognition of dynamic­
addre:ss-translation exceptions for the interruptible
instructions.
A ehange to an active table entry may take effect
for implicit translation any time from the instant of
the change through the completion of the following
purging of the TLB. Wh.en an active table entry is changed, either to
another value suitable for translation, or to a value
that prohibits its use for translation, any subsequent
attempt to use the entry for implicit address transla­
tion before the TLB is purged may yield unpredicta­
ble The use of the new value may begin be­
tween instructions or during execution of an instruc­
tion, including the instruction that caused the
change. Moreover, until the TLB is purged, the TLB
may eontain both the old and the new values, and it
is unpredictable whether the old or new value is se-
66 System/370 Principles of Operation
lected for a particular access. If the use of the new
value of the entry causes an exception, the exception
mayor may not cause an interruption to occur, and
if an interruption does occur, the instruction execu­
tion may be terminated even though the exception
would normally cause suppression or nullification.
Manipulation of attached table entries may cause
spurious table-entry values to be recorded in a TLB.
For example, if changes are made piecemeal, modifi­
cation of a valid attached entry may cause a partially
updated entry to be recorded, and, if an intermediate
value is introduced in the process of the change, a
supposedly invalid entry may temporarily appear
valid and may be recorded in the TLB. Such an in­
termediate value may be introduced if the change is
made by an 110 operation that is retried, or if an
intermediate value is introduced during the execution
of a single instruction.
When LOAD CONTROL changes the segment
size, page size, segment-table address, or segment­
table length, the values of these fields at the start of
the operation are in effect for the duration of the
operation.
The relation between the states of table entries
and their use is summarized in the table "Use of
Translation Tables." PTogranrnmdog When an instruction, such as MOVE (MVC),
changes an attached table entry, including a change
that makes the entry invalid, and subsequently uses
the entry for implicit translation, a changed entry is
being used without a prior purging of the TLB, and
the associated unpredictability of result values and
of exception indication applies.
All modifications to translation tables by the pro­
gram should consider the effect of the TLB on the
use of the tables in main storage and the possible
effects of intermediate result values and of piece­
meal changes. The following rules are recommended
for changing translation tables. If these rules are
observed, translation is performed as if the table
entries from main storage were always used for the
translation process.
1. An entry must not be changed, other than
changing the low-order bit of a page-table en­
try, while it is being used by any CPU. 2. When any change is made to a table entry,
other than a change to the low-order bit of a
page-table entry, each CPU in which the entry
is active must issue PURGE TLB after the
change occurs and prior to the use of the entry
for implicit address translation by that CPU.
Can Copy of Table Entry Be State of Table Entry in TLB ?
Active Attached Valid Yes
Active Attached Invalid Yes
1
Active Unattached Valid Yes
1
Active Unattached Invalid Yes
1 Inactive Attached Valid * Inactive Attached Invalid No Inactive Unattached Valid No Inactive Unattached Invalid No Explanation: Can Table Entry
Be Fetched for Translation ?
Yes
Yes
No
No
*
Yes
No
No
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Can Table Entry Can TLB Copy Be
Be Used for Fetched for Implicit Translation? Translation? Yes Yes
No Yes
No No
No No
No No
No No
No No
1 The TLB may contain a copy of a previously attached and valid entry.
* This state cannot exist. An attached and valid table entry is active. Use of Translation Tables
3. When any change is made to an invalid entry in
such a way as to cause intermediate valid val­
ues to appear in the entry, each CPU to which
the entry is attached must issue PURGE TLB
after the change occurs and prior to the use of
the entry for implicit address translation by
that CPU. Note that when an invalid page-table entry is
made valid introducing intermediate valid
values, the TLB need not be purged in a CPU in
which the entry previously was inactive. Similarly,
when an invalid segment-table entry is made valid
without introducing intermediate valid values, the
TLB need not be purged in a CPU in which the
segment-table entry and all page-table entries
attached by it previously were inactive.
Execution of the PURGE TLB instruction may
have an adverse effect on the performance of some
models. Use of this instruction should, therefore, be
minimized in conformity with the above rules.
Reference and Change Recording
Reference recording provides information for use in
selecting storage blocks for page replacement.
Change recording provides information as to which
pages have to be saved when they are replaced by
new pages. Both reference and change recording are
associated with the dynamic-address-translation
facility.
When the dynamic-address-translation facility is
installed, the key in storage is extended with two
additional bits. Bit 5, the reference bit, normally is
set to one each time a location in the corresponding
storage block is referred to either for storing or
fetching of information. Bit 6, the change bit, is set
to one each time information is stored in the corre­
sponding storage block. The recording of references
and changes is not contingent on whether the CPU is in the extended-control or basic-control mode or
whether address translation is specified.
Reference and change recording takes place for
any main-storage access and applies to accesses
made by a CPU, as well as to those due to II 0 ations. Hence, references to a main-storage location
associated with interruptions and 110 instructions,
such as occur to the CAW, CSW, or PSW locations,
are included. A translation-table lookup in the pro­
cess of address translation is considered a reference, provided the table in main storage has actually been
referred to. It is unpredictable whether updating of
the interval timer causes change and reference bits
for location 80 to be turned on. References to the
operand locations of SET STORAGE KEY, IN­ SERT STORAGE KEY, and RESET REFERENCE
BIT do not cause reference or change to be record­
ed.
The change bit is not turned on for an attempt to
store if the storage reference is not permitted, re­
gardless of whether the CPU instruction responsible
for the reference is suppressed or terminated. In
particular, a CPU reference causing a protection,
addressing, segment-translation, or page-translation
exception, or an 110 reference to an invalid or pro­
tected location does not cause the change bit to be
turned on.
The record of references provided by the refer­
ence bit is substantially accurate. The reference bit
may be turned on by fetching data or instructions
that are neither designated nor used by the program,
and, under certain conditions, a reference may be
made without the reference bit being turned on.
Under certain unusual conditions, a reference bit
that is on may be turned off by other than explicit
program action.
Reference and change recording operates on
2,048-byte blocks regardless of the page size in-
Dynamic Address Translation 67
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