invalid. Similarly, the unit of operation is suppressed
when the exception is encountered during an implicit
reference to a dynamic-address-translation (DAT)
table entry Except for some specific instructions
whose execution is suppressed, the operation is ter­
minated for an operand address that can be translat­
ed but designates an unavailable location. See the
following table for a summary of the action taken on
an addressing exception.
Data in storage remains unchanged unless the
location is available to the CPU. When part of an
operand location is available to the CPU and part is
not, storing may be performed in the available part.
For an invalid operand address or an invalid ad­
dress of a DAT table entry associated with an oper­
and reference, the instruction-length code is 1, 2, or
3, designating the length of the instruction that
caused the reference. However, when the exception
is due to an attempt to store and the address can be
translated but designates an unavailable operand
location, the code on some models may be O. When any part of the location of an instruction is
unavailable or the address of a DAT table entry as­
sociated with an instruction fetch is invalid, the
instruction-length code is 1, 2, or 3, indicating the
number of halfword locations by which the instruc­
tion address has been incremented. It is unpredicta­
ble whether the code is 1, 2, or 3.
Specification Exception
A specification exception is recognized for the fol­
lowing causes:
1. An instruction address does not designate a
location on an even-byte boundary.
2. An operand address does not designate an inte­
gral boundary in an instruction requiring such
integral boundary designation.
3. The block address in SET STORAGE KEY or INSERT STORAGE KEY does not have zeros
in the four low-order bit positions.
4. An odd-numbered general register is designat­
ed by an R field of an instruction that requires
an even-numbered register designation.
5. A floating-point register other than 0, 2, 4, or 6
is specified for a short or long operand, or a
floating-point register other than 0 or 4 is speci­
fied for an extended operand.
6. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
7. The first-operand field is shorter than or equal
to the second-operand field in decimal multipli­
cation or division.
8. Bit positions 8-11 of MONITOR CALL do not
contain zeros.
9. The EC mode is specified (PSW bit 12 is one)
in a CPU that does not have the EC facility
installed. 10. A one is introduced into an unassigned bit
position of the EC-mode PSW (bit positions 0, 2-4,16-17,24-39).
The execution of the instruction identified by the
old PSW is suppressed. However, for causes 9 and 10, the operation that introduces the new PSW is
completed, but an interruption occurs immediately
thereafter.
When the instruction address is odd (cause 1), the
instruction-length code (lLC) is 1,2, or 3, indicating
the number of halfword locations by which the in­
struction address has been incremented. It is unpre­
dictable whether the code is 1, 2, or 3.
For causes 2-8, the ILC is 1,2, or 3, designating
the length of the instruction causing the reference.
When the exception is recognized because of
causes 9 and 10 and the invalid bit value has been
introduced by LOAD PSW or an interruption, the
ILC is O. When the exception due to cause 10 is
Action On Exception
Protection
Exception
Addressing
Exception Explanation: DAT Table Entry Fetch
Suppress
Not applicable. I nstruction Fetch
Suppress
Suppress
Operand Reference
Terminate
1
, but suppress LPSW, SSM, STNSM, STOSM, SCKC, SPT, SPX
Terminate
1
, but suppress LPSW, SSM, STNSM, STOSM, SCKC, SPT, SPX
1 For termination, changes may occur only to result fields. I n this context, "result field" includes condition code, registers,
and storage locations, if any, which are designated to be changed by the instruction. However, no change is made to a
storage location or a key in storage when the reference causes an access exception. Therefore, if an instruction is due to
change only the contents of a field in main storage, and every byte of that field would cause an access exception, the
operation is suppressed.
Summary of Action for Protection and Addressing Exceptions
Interruptions 77

I introduced by SET SYSTEM MASK or STORE THEN OR SYSTEM the ILC is 2. See "Program Status Word" in the chapter "System Control" for a discussion of when the ex­
ceptions associated with the PSW are recognized.
Data Exception
A data exception is recognized when:
1. The sign or digit codes of operands in the
decimal-feature instructions or in CONVERT TO BIN AR Yare invalid.
2. The! operand fields in ADD DECIMAL, COM­ PARE DECIMAL, DIVIDE DECIMAL, MULTIPLY DECIMAL, and SUBTRACT DECIMAL overlap in a way other than with
coincident rightmost or operand fields in ZERO AND ADD overlap, and the rightmost byte of the second operand is to the right of
the rightmost byte of the first operand.
3. The multiplicand in MULTIPLY DECIMAL
has an insufficient number of high-order zeros.
Except for EDIT and EDIT AND MARK, the
operation is suppressed when a sign code is invalid,
regardless of whether any other condition causing
the exception exists; otherwise, the operation is ter­
minated. However, the contents of the sign position
in the rightmost byte of the result field either remain
unchanged or are set to the preferred sign the
contents of the remainder of the result field are un­
predictable.
[n the case of EDIT and EDIT AND MARK, an
invalid sign code is not recognized, and the opera­
tion is terminated on a data exception.
The instruction-length code is 2 or 3.
Programming Note
When, on a program interruption for data exception,
the program finds that a sign code is invalid, the
operation has been suppressed if the following two
conditions are met: • The invalid sign is not located in the numerical
portion of the result field . • The sign code appears in a position specified by
the instruction to be checked for valid sign.
(This condition excludes the first operand of ZERO AND ADD and both operands of EDIT
and EDIT AND MARK.)
An invalid sign code for the rightmost byte of the
result field is not generated when the operation is
terminated. However, an invalid second-operand
sign code is not necessarily preserved when it ap­
pears in the numerical portion of the result field.
78 System/370 Principles of Operation
Fixed-Point-Overflow Exception
A fixed-point-overflow exception is recognized
when a carry occurs out of the high-order bit posi­
tion in fixed-point arithmetic operations, or high­
order significant bits are lost during the algebraic
left-shift operations.
The interruption may be disallowed in the BC
mode by PSW bit 36, and in the EC mode by PSW bit 20. The operation is completed by setting condition
code 3 but otherwise ignoring the information placed
outside the register.
The instruction-length code is 1 or 2.
Fixed-Point-Divide Exception
A fixed-point-divide exception is recognized when in
fixed-point division the divisor is zero or the quo­
tient exceeds the register size, or when the result of CONVERT TO BINARY exceeds 31 bits.
In the case of division, the operation is sup­
pressed. Execution of CONVERT TO BINARY is
completed by ignoring the high-order bits that can­
not be placed in the register.
The instruction-length code is 1 or 2.
Decimal-Overflow Exception
A decimal-overflow exception is recognized when
one or more significant high-order digits are lost
because the destination field in a decimal operation
is too small to contain the result.
The interruption may be disallowed in the BC
mode by PSW bit 37, and in the EC mode by PSW bit 21.
The operation is completed by setting condition
code 3 but otherwise ignoring the overflow informa­
tion.
The instruction-length code is 2 or 3.
Decimal-Divide Exception
A decimal-divide exception is recognized when in
decimal division the divisor is zero or the quotient
exceeds the specified data field size.
The operation is suppressed .
The instruction-length code is 2 or 3.
Exponent-Overflow Exception
An exponent-overflow exception is recognized when
the result characteristic in floating-point addition,
subtraction, multiplication, or division exceeds 127
and the result fraction is not zero.
The operation is completed. The fraction is nor­
malized, and the sign and fraction of the result re­
main correct. The result characteristic is made 128
smaller than the correct characteristic.
The instruction-length code is 1 or 2.