parameters are adjusted such that the execution of
the interrupted instruction is resumed from the point
of interruption when the old PSW stored on the in­
terruption is made the current PSW. It depends on
the instruction how the operand parameters are ad­
justed.
When a unit of operation is suppressed, the in­
struction address in the old PSW designates the next
sequential instruction. The operand parameters,
however, are adjusted so as to indicate the extent to
which instruction execution has been completed. If
the instruction is reexecuted after the conditions
causing the suppression have been removed, the
execution is resumed from the point of interruption.
As in the case of completion and nullification, it
depends on the instruction how the operand parame­
ters are adjusted.
When a unit of operation of an interruptible in­
struction is terminated, the contents, in general, of
any fields due to be changed by the instruction are
unpredictable. On an interruption, the instruction
address in the old PSW designates the next sequen­
tial instruction.
Machine-Check Interruption
The machine-check interruption provides a means
for reporting to the program the oc-currence of
equipment malfunctions. Information is provided to
assist the program in determining the location of the
fault and extent of the damage.
A machine-check interruption causes the old PSW to be stored at location 48 and a new PSW to be
fetched from location 112. When the old PSW spec­
ifies the BC mode, the interruption code and the
instruction-length code in the old PSW are unpredict­
able.
The cause and severity of the malfunction are
identified by a 64-bit machine-check code stored at
location 232. Further information identifying the
cause of the interruption and the location of the fault
may be stored at locations 216-511 and in the area
starting with the location designated by the contents
of control register 15.
Interruption action and the storing of the associ­
ated information are under the control of PSW bit
13 and bits in control register 14. See the chapter
"Machine-Check Handling" for more detailed in­
formation.
Program Interruption
Exceptions resulting from execution of the program,
including the improper specification or use of in­
structions and data, or the detection of a program or
monitor event cause a program interruption. A program interruption causes the old PSW to be
stored at location 40 and a new PSW to be fetched
from location 104. The cause of the interruption is identified by the
interruption code. When the old PSW specifies the
BC mode, the interruption code and the instruction­
length code are placed in the old PSW; when it speci­
fies the EC mode, the interruption code is placed at
locations 142-143, the instruction-length code is
placed in bit positions 5 and 6 of the byte at location
141, with the rest of the bits set to zero, and zeros
are stored at location 140. For some causes addition­
al information identifying the reason for the inter­
ruption is stored in main-storage locations 144-159.
Except for the program-event condition, the con­
dition causing the interruption is identified by a cod­
ed value placed in the rightmost seven bit positions
of the interruption code. Only one condition at a
time can be indicated. Bits 0-7 of the interruption
code are set to zeros.
The program-event condition is indicated by set­
ting bit 8 of the interruption code to one, with bits 0- 7 set to zeros. A program-event condition can be
indicated concurrently with another program inter­
ruption condition, in which case bit 8 is one and the
coded value appears in bit positions 9-15.
A program interruption can occur only when the
corresponding mask bit, if any, is one. The program
mask in the PSW permits masking four of the excep­
tions, bit 1 in control register 0 controls whether SET SYSTEM MASK causes a special-operation
exception, bits 16-31 in control register 8 control
interruptions due to monitor events, and, in the EC
mode, masks are provided for controlling interrup­
tions due to program events. When the mask bit is
zero, the condition is ignored; the condition does not
remain pending.
Programming Note
When the new PSW for a program interruption has 11 format error or causes an exception to be recognized
in the process of instruction fetching, a string of
program interruptions takes place. See "Priority of
Interruptions" for a description of how such strings
are terminated. Some of the conditions indicated as program ex­
ceptions may be recognized also by an I/O opera­
tion, in which case the exception is indicated in the
channel status word.
Program Interruption Conditions
The following is a detailed description of each
program-interruption condition.
Interruptions 75

Operation Exception
An operation exception is recognized when the CPU encounters an instruction with an invalid operatIOn
code. The operation code may not be assigned, or
the instruction with that operation code may not be
available on the CPU. For the purpose of recogniz­
ing an operation exception, the first eight bits of an
instruction, or, when the first eight bits have the
hexadecimal value B2, the first 16 bits form the oper­
ation code.
The operation is suppressed.
The instruction-length code is 1,2, or 3.
Programming Note
In the case of I/O instructions with the values 9C,
9D, and 9E in bit positions 0-7, the value of bit 15 is
used to distinguish between two instructions. Bits
8-14, however, are not checked for zeros, and these
operation codes never cause an operation exception
to be recognized.
To ensure that presently written programs run if
and when the operation codes 9C, 9D, and 9E are
extended further to provide for new functions, only
zeros should be placed in bit positions 8-14. Similar­
ly, zeros should be placed in bit positions 8-15 in the
instruction with the operation code 9F. In accord­
ance with these recommendations, the operation
codes for the seven I/O instructions are shown as 9COO, 9COl, 9DOO, 9DOl, 9EOO, 9EOl, and 9FOO. Some models may offer instructions not listed in
this manual, such as those provided for emulat.ion or
as part of special or custom features. Consequently,
all unlisted operation codes do not necessarily cause
an operation exception to be recognized. Further­
more, as part of the specified operation, these in­
structions may cause modes of operation to be set up
or otherwise alter the system so as to affect the ex­
ecution of subsequent instructions. In order to avoid
the possibility of accidentally causing such operation,
instructions with an unlisted operation code should
be issued only when the specific function associated
with the operation code is desired.
The operation code 00, with a two-byte instruc­
tion format, and the set of sixteen 16-bit operation
codes B2EO to B2EF, with a four-byte instruction
format, allocated for software uses where indica­
tion of invalid operation is required. It is improbable
that these operation codes will ever be assigned to
an instruction implemented in the CPU. Privileged-·Operation Exception
A privileged-operation exception is recognized when
the CPU encounters a privileged instruction in the
problem state.
The operation is suppressed.
76 System/370 Principles of Operation The instruction-length code is 1 or 2.
Execute Exception
The execute exception is recognized when the sub­
ject instruction of EXECUTE is another EXH­ CUTE. The operation is suppressed.
The instruction-length code is 2.
Protection Exception
A protection exception is recognized when the CPU causes a reference to a main-storage location that is
protected against the type of reference, and the key
in storage associated with the location does not
match the protection key in the PSW. The execution of the instruction is suppressed
when the location of the instruction, including the
location of the subject instruction of EXECUTE, is
protected against fetching. Except for some specific
instructions whose execution is suppressed, the oper­
ation is terminated when a protection exception is
encountered during a reference to an operand loca­
tion. See the following table for a summary of the
action taken on a protection exception. On fetching, the protected information is not
loaded into an addressable register or moved to an­
other storage location. When part of an operand
location is protected against storing and part is not,
storing may be performed in the unprotected part.
The contents of a protected location remain un­
changed.
For a protected operand location, the instruction­
length code is 1, 2, or 3, designating the length of
the instruction that caused the reference. However,
for a store-protected operand location, the
instruction-length code on some models may be O. When the location of any part of the instruction is
protected against fetching, the instruction-length
code is 1, 2, or 3, indicating the number of halfwords
by which the instruction address has been incre­
mented. It is unpredictable whether the code is 1, 2,
or 3.
Addressing Exception
An addressing exception is recognized when the CPU causes a reference to a main-storage location
that is not available to the CPU. A main-storage
location is not available to the CPU when the loca­
tion is not provided, when the storage unit is not
configured to the CPU, or when power is off in the
storage unit. An address designating an unavailable
storage location is referred to as invalid.
The execution of the instruction is suppressed
when the address of the instruction, including the
location of the subject instruction of EXECUTE, is