mask, ]PSW bit 7, and external submask bits in con
trol registerO. Each source for an external interrup
tion is assigned a submask bit, and the source can
causean interruption only when the external-mask
bit is one and the corresponding sub mask bit is one.
Theuse of the submask bits does not depend on whether the CPU is in the BC or EC mode. the CPU becomes enabled for a pending
external-interruption condition, the interruption
occurs at the completion of the instruction execution
or interruption that causes the enabling.
More than one source may present a request for
an external interruption at the same time. When theCPU becomes enabled for more than one concur
rently pending request, the interruption occurs for
the pending condition or conditions having the high
est priority.
The highest priority is assigned to the set of con
ditions that includes the interval timer, interrupt key,
and external signals 2 through 7. Within this set, all
pending requests for which theCPU is enabled are
indicated concurrently in the interruption code. Next
in priority are interruption requests for the following
sources, the sources being listed in descending order
ofpriollity: Malfunction alert
Emergency signal
External call
Time-of -day clock sync check
Clock comparatorCPU timer
When more than one emergency-signal or
malfunction-alert request exists at a time, the request
associated with the smallest processor address is
honored first.Only one occurrence each of these
conditions can be indicated at a time in the external
interruption code.
Interval[ Timer
An interruption request for the interval timer is gen
erated when the value of the interval timer is decre
mented from a positive number, including zero, to a
negative number. The request is preserved and re
mains pending in theCPU until it is cleared. The
pending request is cleared when it causes an inter
ruption and byCPU reset.
The condition is indicated by setting bit8 in the
interruption code to one and by setting bits0-7 to
zero. Bits 9-15 are zero unless set to one for another
condition that is concurrently indicated. In the EC
mode, zeros are stored at locations 132-133.
The su bmask bit is located in bit position 24 of
control registerO. This bit is initialized to one.
86 System/370Principles of Operation
Interrupt Key
An interruption request for the interrupt key is gen
erated when the interrupt key on the operator sec
tion of the system control panel is activated. The
request is preserved and remains pending in theCPU until it is cleared. The pending request is cleared
when it causes an interruption and byCPU reset.
The condition is indicated by setting bit 9 in the
interruption code to one and by setting bits0-7 to
zero. Bits 8 and10-15 are zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
The submask bit is located in bit position 25 of
control registerO. This bit is initialized to one.
External Signal
An interruption request for an external signal is gen
erated when a signal is received on one or more of
the signal-in lines.Up to six signal-in lines may be
connected, providing for external signal 2 through
external signal 7. The request is preserved and re
mains pending in theCPU until it is cleared. The
pending request is cleared when it causes an inter
ruption and byCPU reset.
External signals 2 through 7 are indicated by set
ting to one interruption code bits10-15, respective
ly. Bits0-7 are set to zero, and any other bits in the
low-order byte are made zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
All external signals are subject to control by the
submask bit in bit position 26 of control registerO. This bit is initialized to one.
The facility to accept external signals is part of
the direct-control feature.On some models, it is also
available as a separate feature.
Programming Note
The pattern presented in bit positions10-15 of the
interruption code depends on the pattern received
before the interruption is taken. Because of circuit
skew, all simultaneously generated external signals
do not necessarily arrive at the same time, and some
may not be included in the external interruption
resulting from the earliest signals. These late signals
may cause another interruption to be taken.
Malfunction Alert
An interruption request for malfunction alert is gen
erated when anotherCPU that is configured to the CPU enters the check-stop state or loses power. The
request is preserved and remains pending in the re
ceivingCPU until it is cleared. The pending request
is cleared when it causes an interruption and byCPU reset.
trol register
tion is assigned a submask bit, and the source can
cause
bit is one and the corresponding sub mask bit is one.
The
external-interruption condition, the interruption
occurs at the completion of the instruction execution
or interruption that causes the enabling.
More than one source may present a request for
an external interruption at the same time. When the
rently pending request, the interruption occurs for
the pending condition or conditions having the high
est priority.
The highest priority is assigned to the set of con
ditions that includes the interval timer, interrupt key,
and external signals 2 through 7. Within this set, all
pending requests for which the
indicated concurrently in the interruption code. Next
in priority are interruption requests for the following
sources, the sources being listed in descending order
of
Emergency signal
External call
Time-of -day clock sync check
Clock comparator
When more than one emergency-signal or
malfunction-alert request exists at a time, the request
associated with the smallest processor address is
honored first.
conditions can be indicated at a time in the external
interruption code.
Interval[ Timer
An interruption request for the interval timer is gen
erated when the value of the interval timer is decre
mented from a positive number, including zero, to a
negative number. The request is preserved and re
mains pending in the
pending request is cleared when it causes an inter
ruption and by
The condition is indicated by setting bit
interruption code to one and by setting bits
zero. Bits 9-15 are zero unless set to one for another
condition that is concurrently indicated. In the EC
mode, zeros are stored at locations 132-133.
The su bmask bit is located in bit position 24 of
control register
86 System/370
Interrupt Key
An interruption request for the interrupt key is gen
erated when the interrupt key on the operator sec
tion of the system control panel is activated. The
request is preserved and remains pending in the
when it causes an interruption and by
The condition is indicated by setting bit 9 in the
interruption code to one and by setting bits
zero. Bits 8 and
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
The submask bit is located in bit position 25 of
control register
External Signal
An interruption request for an external signal is gen
erated when a signal is received on one or more of
the signal-in lines.
connected, providing for external signal 2 through
external signal 7. The request is preserved and re
mains pending in the
pending request is cleared when it causes an inter
ruption and by
External signals 2 through 7 are indicated by set
ting to one interruption code bits
ly. Bits
low-order byte are made zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
All external signals are subject to control by the
submask bit in bit position 26 of control register
The facility to accept external signals is part of
the direct-control feature.
available as a separate feature.
Programming Note
The pattern presented in bit positions
interruption code depends on the pattern received
before the interruption is taken. Because of circuit
skew, all simultaneously generated external signals
do not necessarily arrive at the same time, and some
may not be included in the external interruption
resulting from the earliest signals. These late signals
may cause another interruption to be taken.
Malfunction Alert
An interruption request for malfunction alert is gen
erated when another
request is preserved and remains pending in the re
ceiving
is cleared when it causes an interruption and by