mask, ]PSW bit 7, and external submask bits in con­
trol register O. Each source for an external interrup­
tion is assigned a submask bit, and the source can
cause an interruption only when the external-mask
bit is one and the corresponding sub mask bit is one.
The use of the submask bits does not depend on whether the CPU is in the BC or EC mode. the CPU becomes enabled for a pending
external-interruption condition, the interruption
occurs at the completion of the instruction execution
or interruption that causes the enabling.
More than one source may present a request for
an external interruption at the same time. When the CPU becomes enabled for more than one concur­
rently pending request, the interruption occurs for
the pending condition or conditions having the high­
est priority.
The highest priority is assigned to the set of con­
ditions that includes the interval timer, interrupt key,
and external signals 2 through 7. Within this set, all
pending requests for which the CPU is enabled are
indicated concurrently in the interruption code. Next
in priority are interruption requests for the following
sources, the sources being listed in descending order
of priollity: Malfunction alert
Emergency signal
External call
Time-of -day clock sync check
Clock comparator CPU timer
When more than one emergency-signal or
malfunction-alert request exists at a time, the request
associated with the smallest processor address is
honored first. Only one occurrence each of these
conditions can be indicated at a time in the external­
interruption code.
Interval[ Timer
An interruption request for the interval timer is gen­
erated when the value of the interval timer is decre­
mented from a positive number, including zero, to a
negative number. The request is preserved and re­
mains pending in the CPU until it is cleared. The
pending request is cleared when it causes an inter­
ruption and by CPU reset.
The condition is indicated by setting bit 8 in the
interruption code to one and by setting bits 0-7 to
zero. Bits 9-15 are zero unless set to one for another
condition that is concurrently indicated. In the EC
mode, zeros are stored at locations 132-133.
The su bmask bit is located in bit position 24 of
control register O. This bit is initialized to one.
86 System/370 Principles of Operation
Interrupt Key
An interruption request for the interrupt key is gen­
erated when the interrupt key on the operator sec­
tion of the system control panel is activated. The
request is preserved and remains pending in the CPU until it is cleared. The pending request is cleared
when it causes an interruption and by CPU reset.
The condition is indicated by setting bit 9 in the
interruption code to one and by setting bits 0-7 to
zero. Bits 8 and 10-15 are zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
The submask bit is located in bit position 25 of
control register O. This bit is initialized to one.
External Signal
An interruption request for an external signal is gen­
erated when a signal is received on one or more of
the signal-in lines. Up to six signal-in lines may be
connected, providing for external signal 2 through
external signal 7. The request is preserved and re­
mains pending in the CPU until it is cleared. The
pending request is cleared when it causes an inter­
ruption and by CPU reset.
External signals 2 through 7 are indicated by set­
ting to one interruption code bits 10-15, respective­
ly. Bits 0-7 are set to zero, and any other bits in the
low-order byte are made zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
All external signals are subject to control by the
submask bit in bit position 26 of control register O. This bit is initialized to one.
The facility to accept external signals is part of
the direct-control feature. On some models, it is also
available as a separate feature.
Programming Note
The pattern presented in bit positions 10-15 of the
interruption code depends on the pattern received
before the interruption is taken. Because of circuit
skew, all simultaneously generated external signals
do not necessarily arrive at the same time, and some
may not be included in the external interruption
resulting from the earliest signals. These late signals
may cause another interruption to be taken.
Malfunction Alert
An interruption request for malfunction alert is gen­
erated when another CPU that is configured to the CPU enters the check-stop state or loses power. The
request is preserved and remains pending in the re­
ceiving CPU until it is cleared. The pending request
is cleared when it causes an interruption and by CPU reset.
Facilities are provided for holding a separate
malfunction-alert request pending in the receiving CPU for each other configured CPU. Configuring a CPU out of the system does not generate a
malfunction-alert condition.
The condition is indicated by an external­
interruption code of 1200 (hex). The processor
address of the CPU that generated the condition is
stored at locations 132-133.
The subclass mask bit is located in bit position 16
of control register O. This bit is initialized to zero.
Emergency Signal
An interruption request for emergency signal is gen­
erated when the CPU accepts the emergency-signal
order specified by a SIGNAL PROCESSOR instruc­
tion addressing this CPU. The instruction may have
been executed by this CPU or by another CPU con­
figured to this CPU. The request is preserved and
remains pending in the receiving CPU until it is
cleared. The pending request is cleared when it caus­
es an interruption and by CPU reset.
Facilities are provided for holding a separate
emergency-signal request pending in the receiving CPU for each configured CPU, including the receiv­
ing CPU itself.
The condition is indicated by an external­
interruption code of 1201 (hex). The processor
address of the CPU that issued the SIGNAL PRO­ CESSOR instruction is stored at locations 132-133.
The subclass mask bit is located in bit position 17
of control register o. This bit is initialized to zero.
External Call
An interruption request for external call is generated
when the CPU accepts the external-call order speci­
fied by a SIGNAL PROCESSOR instruction ad­
dressing this CPU. The instruction may have been
executed by this CPU or by another CPU configured
to this CPU. The request is preserved and remains
pending in the receiving CPU until it is cleared. The
pending request is cleared when it causes an inter­
ruption and by CPU reset. Only one external-call request, along with the
processor address, may be held pending in a CPU at
a time.
The condition is indicated by an external­
interruption code of 1202 (hex). The processor
address of the CPU that issued the SIGNAL PRO­ cEssoR instruction is stored at locations 132-133.
The subclass mask bit is located in bit position 18
of control register o. This bit is initialized to zero.
Time-or-Day Clock Sync Check
The time-of-day (TOD) clock sync check condition
indicates that more than one TOD clock exists in the
configuration, and that the low-order 32 bits of the
clocks are not running in synchronism.
An interruption request for TOD clock sync
check exists when the clock accessed by this CPU is
running, the clock accessed by any other CPU con­
figured to this CPU is running, and bits 32-63 of the
two clocks do not match. ,When a clock enters the
running state, or a running clock is added to the
configuration, a delay of up to 1.048576 seconds (2
20
microseconds) may occur before the mismatch
condition is recognized.
When only two clocks are in the configuration
and either or both of the clocks are in the error,
stopped, or not-operational state, it is unpredictable
whether a TOD clock sync check condition is recog­
nized, and, if it is recognized, it may continue to
persist up to 1.048576 seconds after both clocks
have been running with low-order bits matching.
However, in this case, the condition does not persist
if the two CPU s are configured apart.
When more than one CPU shares a TOD clock,
only the CPU with the smallest processor address
among those sharing the clock indicates a sync­
check condition associated with that clock.
If the condition responsible for the request is re­
moved before the request is honored, the request
does not remain pending, and no interruption occurs.
Conversely, the request is not cleared by the inter­
ruption, and, if the condition persists, more than one
interruption may result from a single occurrence of
the condition.
The condition is indicated by an external­
interruption code of 1003 (hex). In the EC mode,
zeros are stored at locations 132-133.
The subclass mask bit is located in bit position 19
of control register O. This bit is initialized to zero.
Clock Comparator
An interruption request for the clock comparator
exists whenever either of the following conditions is
met:
1. The time-of-day clock is running, and the value
of the clock comparator is less than the value
in the compared portion of the time-of -day
clock, both comparands being considered bina­
ry unsigned quantities.
2. The clock comparator is installed, and the tim.e­
of-day clock is in the error state or not opera­
tional.
If the condition responsible for the request is re­
moved before the request is honored, the request
does not remain pending, and no interruption occurs.
Interruptions 87
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