2. External call and emergency signal cause the
corresponding interruption conditions to be
generated. External call can be rejected be
cause of a previously generated external-call
condition.
3.Start sets condition code ° and has no other
effect.
4.Stop causes the CPU to set condition code 0, take pending interruptions for which it is ena
bled, and enter the stopped state.
S. Restart provides a means to store the currentPSW. Two CPUs can simultaneously execute SIGNAL PROCESSOR instructions, with each CPU address
ing the other. When this occurs, oneCPU, but not
both, can find the access path busy because of the
transmission of the order code or status bits associat
ed with theSIGNAL PROCESSOR instruction that
is being executed by the otherCPU. Alternatively,
bothCPUs can find the access path available and
transmit the order codes to each other. In particular,
twoCPUs can simultaneously stop, restart, or reset
each other.
TOO Clock Synchronization
In an installation with more than oneCPU, depend
ing on the model, eachCPU may have a separate
time-of -day clock, or more than oneCPU may share
a clock. In all cases, eachCPU accesses a single
clock. A configuration change does not affect the
value in any of the clocks or which clock aCPU accesses.
When more than one time-of-day clock exists in a
configured system, the stepping rates are synchro
nized such that all time-of-day clocks in the configu
ration are incremented at the exact same rate. TheCPU timer in each CPU is also decremented at this
same rate.
The TOD-clock-synchronization facility provides
functions that make it possible to write a single
model-independent supervisor clock-synchronization
program which can handle systems with a single
time-of-day clock or with multiple clocks. Addition
ally, the facility, in conjunction with the supervisor
clock-synchronization program, provides, in effect,
only one clock in a multiprocessing system, so that,
to all programs storing the clock, it appears that allCPUs read the same clock.
The synchronization is provided by a mechanism
which causes a stopped clock to start incrementing in
response to a signal from another clock and which
checks whether the low-order 32 bits of all clocks in
the configuration are stepped at the same time.
Lack of synchronization is signaled by an external
interruption indicating the TOD-clock-sync-check
condition. The synchronization is under control of
the TOD-clock-sync-control bit in control register0, bit position 2. See "Time-of-Day Clock Sync Check" in the chapter "Interruptions" and "Time-of Day Clock" in the chapter "System Control." Programming Note . A stopped clock, with the TOD-clock-sync-control
bit set to one, starts when bits 32-63 of any running
clock in the configuration are incremented to zero.
This permits the program to synchronize all clocks to
any particular clock without requiring special opera
tor action to select a"master clock" as the source of
the clock synchronization pulses. The supervisor
clock-synchronization program must check for syn
chronization of high-order bits and assist in syn
chronizing clocks by communicating the high-order
bit values and setting them in the clocks to be syn
chronized.CPU Address Identification
EachCPU in a multiprocessor installation is as
signed a unique address. TheCPU is designated by
specifying this address in the processor address field
of aSIGNAL PROCESSOR instruction. The CPU signaling a malfunction alert, emergency signal, or
external call is identified by storing this address in
the processor-address field with the interruption.
TheCPU address is assigned during system installa
tion and is not changed as a result of configuration
changes. The program can determine the address of
theCPU by means of the instruction STORE CPU ADDRESS. Multiprocessing 101
corresponding interruption conditions to be
generated. External call can be rejected be
cause of a previously generated external-call
condition.
3.
effect.
4.
bled, and enter the stopped state.
S. Restart provides a means to store the current
ing the other. When this occurs, one
both, can find the access path busy because of the
transmission of the order code or status bits associat
ed with the
is being executed by the other
both
transmit the order codes to each other. In particular,
two
each other.
TOO Clock Synchronization
In an installation with more than one
ing on the model, each
time-of -day clock, or more than one
a clock. In all cases, each
clock. A configuration change does not affect the
value in any of the clocks or which clock a
When more than one time-of-day clock exists in a
configured system, the stepping rates are synchro
nized such that all time-of-day clocks in the configu
ration are incremented at the exact same rate. The
same rate.
The TOD-clock-synchronization facility provides
functions that make it possible to write a single
model-independent supervisor clock-synchronization
program which can handle systems with a single
time-of-day clock or with multiple clocks. Addition
ally, the facility, in conjunction with the supervisor
clock-synchronization program, provides, in effect,
only one clock in a multiprocessing system, so that,
to all programs storing the clock, it appears that all
The synchronization is provided by a mechanism
which causes a stopped clock to start incrementing in
response to a signal from another clock and which
checks whether the low-order 32 bits of all clocks in
the configuration are stepped at the same time.
Lack of synchronization is signaled by an external
interruption indicating the TOD-clock-sync-check
condition. The synchronization is under control of
the TOD-clock-sync-control bit in control register
bit set to one, starts when bits 32-63 of any running
clock in the configuration are incremented to zero.
This permits the program to synchronize all clocks to
any particular clock without requiring special opera
tor action to select a
the clock synchronization pulses. The supervisor
clock-synchronization program must check for syn
chronization of high-order bits and assist in syn
chronizing clocks by communicating the high-order
bit values and setting them in the clocks to be syn
chronized.
Each
signed a unique address. The
specifying this address in the processor address field
of a
external call is identified by storing this address in
the processor-address field with the interruption.
The
tion and is not changed as a result of configuration
changes. The program can determine the address of
the