Purge TLB PTLB [S] 8200 o 16 31
All information in the translation-Iookaside buffer
(TLB) of this CPU is made invalid. No change is
made to the contents of addressable storage or regis­
ters.
The TLB appears cleared of its original contents
for all following instructions. When the CPU does
not have a TLB, the instruction is equivalent to a
no-operation. The invalidation is not signaled to any
other CPU. A serialization function is performed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs. No subsequent
instructions, their operands, or dynamic-address­
translation entries are fetched by this CPU until the
execution of this instruction is complete.
Bits 16-31 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the translation feature is not in­
stalled)
Privileged operation
Read Direct
RDD [SI] 85
o 8 16 20 31
The contents of the 12 field are made available as
signal-out timing signals. A direct-in data byte is
accepted from an external device in the absence of a
hold signal and is placed in the location designated
by the operand address.
The contents of the 12 field are made available on
a set of eight signal-out lines as 0.5-microsecond to
1.0-microsecond timing signals. These signal-out
lines are also used in WRITE DIRECT. On a ninth
line (read out) a 0.5-microsecond to 1.0- microsecond timing signal is made available coinci­
dent with these timing signals. The read-out line is
distinct from the write-out line in WRITE DIRECT.
No checking bits are made available with the eight
instruction bits.
Eight data bits are accepted from a set of eight
direct-in lines when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least 0.5 microsecond. No checking bits
are accepted with data signals, but a checking-block
code is generated as the data is placed in storage.
When the hold signal is not removed, the CPU does
not complete the instruction.
A serialization function is performed before the
signals are made available and again after the first­
operand byte is placed in storage. CPU operation is
delayed until all previous accesses by this CPU to
main storage have been completed, as observed by
channels and other CPUs, and then the signal-out
timing signals are presented. No subsequent instruc­
tions or their operands are accessed by this CPU until the first operand byte has been placed in main
storage, as observed by channels and other CPUs. An excessively long instruction execution may
result in incomplete updating of the interval timer.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the direct-control feature is not
installed)
Privileged operation
Access (store, operand 1)
Reset Reference Bit
RRB [S] 8213
o 16 20 31
The reference bit is set to zero in the key in storage
associated with the block that is designated by the
second-operand address.
Bits 8-20 of the second-operand address desig­
nate a block of 2,048 bytes in real main storage. Bits 0-7 and 21-31 of the address are ignored.
The address designating the storage block, being a
real address, is not subject to dynamic address trans­
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The value of the remaining bits of the key, includ­
ing the change bit, is not affected.
System-Control Instructions 107
The condition code is set to reflect the state of
the reference and change bits before the reference
bit is set to zero.
Resulting Condition Code:
o Reference bit zero, change bit zero
1 Reference bit zero, change bit one
2 Reference bit one, change bit zero
3 Reference bit one, change bit one
Program Exceptions: Operatilon (if the translation feature is not in­
stalled) Privileged operation
Access (addressing for operand access only, oper­
and 2)
Set Clock [S] C==._B2_04 __ __ D_2 o 16 20 31
The current value of the time-of -day clock is re­
placed by the contents of the doubleword designated
by the second-operand address, and the clock is
placed in the stopped state.
The operand designated by the instruction is con­
sidered an unsigned, 64-bit, fixed-point This operand replaces the contents of the clock, as
determined by the clock's resolution. Only those bits
of the operand are set in the clock that correspond
to the bit positions to be updated by the clock; the
contents of the remaining rightmost bit positions are
not preserved in the clock and are ignored.
After the clock value is set, the clock is placed in
the stopped state. The clock leaves the stopped state
to enter the set state and resume counting under control of the time-of -day clock control bi1c (control register 0, bit 2). When the bit
is zero or the clock-synchronization facility is not
installed, the clock enters the set state at the cO!11ple­ tion of the instruction. When the bit is one, the
clock remains in the stopped state either until the bit
is set to zero or until any other running time-oI-day
clock in the configured system is incremented to a
value of aU zeros in bit positions 32-63.
The value of the clock is changed, and the clock is
placed in the stopped state only if the TOD-clock
switch on the system console is in the enable-set
position. If the switch is in the secure position, the
value and the state of the clock are not changed. The
two results are distinguished by condition codes 0 108 System/370 Principles of Operation
and 1, respectively. When the clock is not opera­
tional, regardless of the setting of the TOD-clock
switch, the value and the state of the clock are not
changed, and condition code 3 is set.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. Access
exceptions are recognized regardless of the state of
the clock and the setting of the TOD-clock switch.
Resulting Condition Code:
o Clock value set
1 Clock value secure
2 -
3 Clock not operational
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Set Clock Comparator SCKC [S] B206 o 16 20 31
The current value of the clock comparator is re­
placed by the contents of the doubleword designated
by the second-operand address. Only those bits of the operand are set in the clock
comparator that correspond to the bit positions to be
compared with the time-of -day clock; the contents
of the remaining rightmost bit positions are ignored
and are not preserved in the clock comparator.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the clock comparator is not in-
stalled)
Privileged operation
Access (fetch, operand 2)
Specification
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