Purge TLB PTLB [S] 8200 o 16 31
All information in the translation-Iookaside buffer
(TLB) of thisCPU is made invalid. No change is
made to the contents of addressable storage or regis
ters.
The TLB appears cleared of its original contents
for all following instructions. When theCPU does
not have a TLB, the instruction is equivalent to a
no-operation. The invalidation is not signaled to any
otherCPU. A serialization function is performed. CPU oper
ation is delayed until all previous accesses by thisCPU to main storage have been completed, as ob
served by channels and otherCPUs. No subsequent
instructions, their operands, or dynamic-address
translation entries are fetched by thisCPU until the
execution of this instruction is complete.
Bits 16-31 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the translation feature is not in
stalled)
Privileged operation
Read Direct
RDD[SI] 85
o 8 1620 31
The contents of the12 field are made available as
signal-out timing signals. A direct-in data byte is
accepted from an external device in the absence of a
hold signal and is placed in the location designated
by the operand address.
The contents of the12 field are made available on
a set of eight signal-out lines as 0.5-microsecond to
1.0-microsecond timing signals. These signal-out
lines are also used in WRITE DIRECT.On a ninth
line (read out) a 0.5-microsecond to1.0- microsecond timing signal is made available coinci
dent with these timing signals. The read-out line is
distinct from the write-out line in WRITE DIRECT.
No checking bits are made available with the eight
instruction bits.
Eight data bits are accepted from a set of eight
direct-in lines when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least0.5 microsecond. No checking bits
are accepted with data signals, but a checking-block
code is generated as the data is placed in storage.
When the hold signal is not removed, theCPU does
not complete the instruction.
A serialization function is performed before the
signals are made available and again after the first
operand byte is placed in storage.CPU operation is
delayed until all previous accesses by thisCPU to
main storage have been completed, as observed by
channels and otherCPUs, and then the signal-out
timing signals are presented. No subsequent instruc
tions or their operands are accessed by thisCPU until the first operand byte has been placed in main
storage, as observed by channels and otherCPUs. An excessively long instruction execution may
result in incomplete updating of the interval timer.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the direct-control feature is not
installed)
Privileged operation
Access (store, operand 1)
Reset Reference Bit
RRB[S] 8213
o 1620 31
The reference bit is set to zero in the key in storage
associated with the block that is designated by the
second-operand address.
Bits8-20 of the second-operand address desig
nate a block of 2,048 bytes in real main storage. Bits0-7 and 21-31 of the address are ignored.
The address designating the storage block, being a
real address, is not subject to dynamic address trans
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The value of the remaining bits of the key, includ
ing the change bit, is not affected.
System-Control Instructions107
All information in the translation-Iookaside buffer
(TLB) of this
made to the contents of addressable storage or regis
ters.
The TLB appears cleared of its original contents
for all following instructions. When the
not have a TLB, the instruction is equivalent to a
no-operation. The invalidation is not signaled to any
other
ation is delayed until all previous accesses by this
served by channels and other
instructions, their operands, or dynamic-address
translation entries are fetched by this
execution of this instruction is complete.
Bits 16-31 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the translation feature is not in
stalled)
Privileged operation
Read Direct
RDD
o 8 16
The contents of the
signal-out timing signals. A direct-in data byte is
accepted from an external device in the absence of a
hold signal and is placed in the location designated
by the operand address.
The contents of the
a set of eight signal-out lines as 0.5-microsecond to
1.0-microsecond timing signals. These signal-out
lines are also used in WRITE DIRECT.
line (read out) a 0.5-microsecond to
dent with these timing signals. The read-out line is
distinct from the write-out line in WRITE DIRECT.
No checking bits are made available with the eight
instruction bits.
Eight data bits are accepted from a set of eight
direct-in lines when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least
are accepted with data signals, but a checking-block
code is generated as the data is placed in storage.
When the hold signal is not removed, the
not complete the instruction.
A serialization function is performed before the
signals are made available and again after the first
operand byte is placed in storage.
delayed until all previous accesses by this
main storage have been completed, as observed by
channels and other
timing signals are presented. No subsequent instruc
tions or their operands are accessed by this
storage, as observed by channels and other
result in incomplete updating of the interval timer.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the direct-control feature is not
installed)
Privileged operation
Access (store, operand 1)
Reset Reference Bit
RRB
o 16
The reference bit is set to zero in the key in storage
associated with the block that is designated by the
second-operand address.
Bits
nate a block of 2,048 bytes in real main storage. Bits
The address designating the storage block, being a
real address, is not subject to dynamic address trans
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The value of the remaining bits of the key, includ
ing the change bit, is not affected.
System-Control Instructions