Set CPU Timer
[S] 8208 o 16 20 The current value of the CPU timer is replaced by
the contents of the doubleword designated by the
second-operand address.
31 Only those bits of the operand are set in the CPU timer that correspond to the bit positions to be up­
dated; the contents of the remaining rightmost bit
positions are ignored and are not preserved in the CPU timer.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions: Operation (if the CPU timer is not installed)
Privileged operation
Access (fetch, operand 2)
Specification
Set Prefix SPX [S] 8210 o 16 20 31
The contents of the prefix register are replaced by
the contents of bit positions 8-19 of the word at the
location designated by the second-operand address.
All information in the translation-Iookaside buffer
(TLB) of this CPU is made invalid.
If the operation is completed, the new prefix is
used for any interruptions following the execution of
the instruction and for the execution of subsequent
instructions. The contents of bit positions 0-7 and 20-31 of the operand are ignored.
The TLB, if the CPU has one, appears cleared of
its original contents for all following instructions.
A serialization function is p.erformed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs. No subsequent
instructions, operands, or dynamic-address-
translation entries are fetched by this CPU until the
execution of this instruction is completed.
The operand must be designated on a word
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions: Operation (if the multiprocessing feature is not
installed)
Privileged operation
Access (fetch, operand 2)
Specification
Set PSW Key From Address SPKA [S] 820A o 16 20 The four-bit protection key of the current PSW is
replaced by bits 24-27 of the operand address.
The second-operand address is not used to ad­
dress data; instead, bits 24-27 of the address form
the new key. Bits 8-23 and 28-31 of the second­
operand address are ignored.
Resulting Condition Code: The code remains un­
changed.
Program Exceptions: 31 Operation (if the PSW -key-handling feature is not
installed)
Privileged operation
Programming Notes
The format of the SPKA instruction permits the
program to set the protection key either from the
general register designated by the B2 field or from
the D2 field in the instruction itself.
When a problem program requests the supervisor
program to access a location specified by the prob­
lem program, the SPKA instruction can be used by
the supervisor program to verify that the problem
program is authorized to make this access, provided
the supervisor program is not protected against
fetching. The supervisor program can perform the
verification by replacing the PSW key of the supervi­
sor program with the problem-program key before
making the access and subsequently restoring the
System-Control Instructions 109

supervisor-program PSW key to its original value.
Caution must be observed, however, in handling any
resulting protection exceptions since such exceptions
may cause the operation to be terminated and, on
some models, the resulting interruption may be de­
layed and indicated with an instruction-length code
of zero.
Set Storage Key SSK [RR]
o 8 12 15
The key in storage associated with the block that is
addressed by the contents of the register designated
by the R2 field is replaced by the contents of the
register designated by the Rl field.
Bits 8-20 of the register designated by the R2
field designate a block of 2,048 bytes in real main
storage. Bits 0-7 and 21-27 of the registerarc ig­
nored. Bits 28-31 of the register must be zeros; oth­
erwise, a specification exception is recognized, and
the operation is suppressed.
The address designating the storage block, being a
real address, is not subject to dynamic address trans­
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The seven-bit key is obtained from bit positions 24-30 of the register designated by the Rl field. The
contents of bit positions 0-23 and 31 of the register
are ignored. When dynamic address translation is not
installed, bits 29 and 30 are ignored.
Condition Code: The code remains unchanged.
Program Exceptiom:
Privileged operation
Access (addressing for operand access only, oper­
and 2)
Specification
110 Systern/370 Principles of Operation Set System Mask SSM [S] 80 o 8 16 20 31
Bits 0-7 of the current PSW are replaced by the byte
at the location designated by the second-operand
address.
When the SSM-suppression facility is installed,
the execution of the instruction is subject to the
SSM-suppression bit, bit 1 of control register O. When the bit is zero, the instruction is executed nor­
mally. When the bit is one and the CPU is in the
supervisor state, a special-operation exception is
recognized, and the operation is suppressed.
The operation is suppressed on protection and
addressing exceptions.
The value to be loaded into the PSW is not
checked for validity before loading. However, im­
mediately after loading, a specification exception is
recognized, and a program interruption occurs, if the CPU is in the EC mode and the contents of bit posi­
tions 0 and 2-4 of the PSW are not all zeros. In this
case, the instruction is completed, and the
instruction-length code is set to 2.
Bits 8-15 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Special operation
Signal Processor SIGP AE
o 8 12 16 [RS] 20 31
An eight-bit order code is transmitted to the CPU designated by the processor address contained in the
third operand. The result is indicated by the condi­
tion code and may be detailed by status assembled in
the first-operand location.
The second-operand address is not used to ad­
dress data; instead, bits 24-31 of the address contain
the eight-bit order code. Bits 8-23 of the second­
operand address are ignored. The order code speci­
fies the function to be performed by the addressed