Programming Notes
The program should allow for the possibility that the CPU identification number may contain the digits
A-F as well as the digits 0-9. The principal uses of the information stored by
the instruction STORE CPU ID are the following:
1. The CPU identification number, combined with
the model number, provides a unique CPU identification that can be used in associating
results with an individual system, particularly
in regard to functional differences, perform­
ance differences, and error handling.
2. The model number, in conjunction with the
version code, can be used by model­
independent programs in determining which
model-dependent recovery programs should be
called.
3. The MCEL length can be used by model­
independent programs to allocate main storage
for the MCEL area.
Store CPU Timer
[S] 8209 o 16 20 The current value of the CPU timer is stored at the
double word designated by the second-operand ad­
dress.
31
Zeros are provided for the rightmost bit positions
that are not updated by the CPU timer.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the CPU timer is not installed)
Privileged operation
Access (store, operand 2)
Specification
Store Prefix
[S]
8211
o 16 20 31
The contents of the prefix register are stored at the
word location designated by the second-operand
address. Zeros are provided for bit positions 0-7 and 20-31. The operand must be designated on a word
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the multiprocessing feature is not
installed)
Privileged operation
Access (store, operand 2)
Specification
Store Then AND System Mask
[SI]
AC 12 8,
o 8 16 20 D, 31
Bits 0-7 of the current PSW are stored at the first­
operand location. Then the contents of bit positions 0- 7 of the current PSW are replaced by the logical
product (AND) of their original contents and the
second operand.
The operation is suppressed on protection and
addressing exceptions.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the translation feature is not in­
stalled)
Privileged operation
Programming Note
The STORE THEN AND SYSTEM MASK instruc­
tion permits the program to turn off selected bits in
the system mask while retaining the original contents
for later restoration. For example, in EC mode it
System-Control Instructions 113

may be necessary that a program, which is not aware
of the present status, disable program-event record­
ing for a few instructions.
Store Then OR System Mask STOSM [SI] _1 2 ------,----S, ""::-::--1 _D 1 . :=J o 8 16 20 31
Bits 0-7 of the current PSW are stored at the first­
operand location. Then the contents of bit positions 0- 7 of the current PSW are replaced by the logical
sum (OR) of their original contents and the second
operand.
The value to be loaded into the PSW is not
checked for validity before loading. However, im­
mediately after loading, a specification exception is
recognized, and a program interruption occurs, if the CPU is in the EC mode and the contents of bit posi­
tions 0 and 2-4 of the PSW are not all zeros. In this
case, the instruction is completed, and the
instruction-length code is set to 2.
The operation is suppressed on prote9tion and
addressing exceptions.
Condition Code: The code remains unchangcd.
Program Exceptions:
Operation (if the translation feature is not in-
stalled) Privileged operation
Access (store, operand 1)
Specification
Programming Note
The STORE THEN OR SYSTEM MASK instruc­
tion permits the program to turn on selected bits in
the system mask while retaining the original contents
for later restoration. For example, in EC mode the
program may desire to enable the CPU for I/O in­
terruptions and yet may not know the current status
of the external-mask bit.
114 System/370 Principles of Operation
Write Direct
WRD Dt (Bt),I2 [SI]
84 I2 I B, I D, 0 8 16 20 31
The byte at the location designated by the operand
address is made available as a set of direct-out static
signals. Eight instruction bits are made available as
signal-out timing signals.
The eight data bits of the bytc fetched from stor­
age are presented on a set of eight direct-out lines as
static signals. These signals remain until the next
WRITE DIRECT is executed. No checking bits are
presented with the eight data bits.
The contents of the h field are made available
simultaneously on a set of eight signal-out lines as
0.5-microsecond to 1.0-microsecond timing signals. On a ninth line (write out), a 0.5-microsecond to
1.0-microsecond timing signal is made available con­
currently with these timing signals. The eight signal­
out lines are also used in READ DIRECT. No
checking bits are made available with the eight in­
struction bits.
A serialization function is performed before the
operand is fetched and again after the signals have
been presented. CPU operation is delayed until all I previous accesses by this CPU to main storage have
been completed, as observed by channels and other CPUs, and then the first operand byte is fetched and
the signals made available. No subsequent instruc- I tions or their operands are fetched by this CPU until
the signals have been made available.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the direct-control feature is not
installed)
Privileged operation
Access (fetch, operand 1) I