CPU. The assignment and definition of order codes
appears in the chapter "Multiprocessing." The 16-bit binary number contained in bit posi­
tions 16-31 of the general register designated by the
R3 field forms the processor address. The high-order
16 bits of the register are ignored.
A serialization function is performed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs, and then the
signaling occurs. No subsequent instructions or their
operands are accessed by this CPU until the execu­
tion of the instruction is completed.
When the order code is accepted and no nonzero
status is returned, condition code 0 is set. When
status information is generated by this CPU or re­
turned by the addressed CPU, the status is placed in
the general register designated by the Rl field, and
condition code 1 is set.
When the access path to the addressed CPU is
busy or the addressed CPU is operational and in a
state where it cannot respond to the order code,
condition code 2 is set.
When the addressed CPU is not operational (that
is, it is not provided, or it is not configured to this
CPU, or it is in certain customer-engineer test modes,
or its power is off), condition code 3 is set.
A more detailed discussion of the condition-code
settings for SIGNAL PROCESSOR is contained in
the chapter "Multiprocessing." Resulting Condition Code:
o Order code accepted
1 Status stored
2 Busy
3 Not operational Program Exceptions:
Operation (if the multiprocessing feature is not
installed)
Privileged operation
Programming Notes
The execution time on the issuing CPU for SIG­ NAL PROCESSOR may vary depending on the
model, the order code, and the state of the addressed
CPU. In some cases, the execution time may be sev­
eral seconds.
To ensure that presently written programs will be
executed properly when new facilities using addi­
tional bits are installed, only zeros should appear in
the unused bit positions of the second-operand ad­
dress and in bit positions 0-15 of the register desig-
nated by the R3 field. Store Clock Comparator 8207 o 16 20 31
The current value of the clock comparator is stored
at the doubleword designated by the second-operand
address.
Zeros are provided for the rightmost bit positions
that are not used for comparison with the time-of­
day clock.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the clock comparator is not in-
stalled)
Privileged operation
Access (store, operand 2)
Specification Store Control
STCTL Rl,R3,D2(B2) I B6
o 8 12 16 [RS] 20 31
The set of control registers starting with the control
register designated by the Rl field and ending with
the control register designated by the R3 field is
stored at the locations designated by the second­
operand address.
The storage area where the contents of the con­
trol registers are placed starts at the location desig­
nated by the second-operand address and continues
through as many storage words as the number of
control registers specified. The contents of the con­
trol registers are stored in ascending order of their
addresses, starting with the control register designat­
ed by the Rl field and continuing up to and includ­
ing the control register designated by the R3 field,
with control register 0 following control register 15.
The contents of the control registers remain un­
changed.
System-Control Instructions 111

An attempt is made to store each of the designat­
ed control registers, regardless of whether the facility
requiring the presence of the control register is in­
stalled. \Vhenever the storage reference causes an
access exception, the exception is indicated. The
information provided for control register positions
not associated with an installed facility is unpredicta­
ble.
The second operand must be designated on a
word boundary; otherwise, a specification exception
is recognized, and the operation is suppressed.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (store, operand 2)
Specification
Programmiing Note
Although on some CPUs STORE CONTROL may
provide zeros in the bit positions corresponding to
the unassigned register positions, the program should
not depend on such zeros.
Store CPU Address
STAP [S]
[ __ B_2_1_2 ______ __ _____ D_2 __ o 16 20 31
The processor address by which this CPU is identi­
fied in a multiprocessing system is stored at the half­
word location designated by the second-operand
address.
The operand must be designated on a halfword
boundary; otherwise, a specifIcation exception is
recognized, and the operation is suppressed. The
operation :is suppressed on protection and. addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions: Operation (if the multiprocessing feature is no; installed)
Privileged operation
Access (store; operand 2)
Specification
112 System/370 Principles of Operation
Store CPU ID
STIDP [S] B202 o 16 20 Information identifying the CPU is stored at the
doubleword location designated by the second­
operand address.
The format of the information is as follows:
Version Code CPU Identification Number
o 8
31
31 Model Number Maximum MeEL Length I 32 48 63
The version-code field, bit positions 0-7, contains
model-dependent information, not otherwise easily
obtained, that is normally of importance only in
model-dependent recovery or diagnostic programs.
Bit positions 8-31 contain the CPU identification
number, consisting of six digits: a high-order zero
digit and five digits selected from the physical serial
number stamped on the CPU, or six digits selected
from the serial number. The contents of the CPU identification-number field, in conjunction with the
model number, permit unique identification of the CPU. Bit positions 32-47 contain the model number,
consisting of four digits: a high-order zero digit and
the three digits of the model number, such as 0145 or 0168. Bit positions 48-63 contairt a 16-bit binary value
indicating the length in bytes of the longest machine­
check extended logout (MCEL) that can be stored
by the CPU. The operand must be designated on a dotibleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation . Access (store, operand 2)
Specification