ADD
ADD
Name
ADD HALFWORD
ADD LOGIGAL ADD LOGIGAL Mnemonic
AR
A
AH
ALR
AL
NR
RR C RX C RX C RR C RX C RR C AND
AND N
RX C AND (character) AND (immediate) BRANCH AND LINK NC SS C NI SI C BALR RR
BAL BCR RX
RR BRANCH AND LINK BRANCH ON CONDITION BRANCH ON CONDITION BRANCH ON COUNT BRANCH ON COUNT BC RX BCTR RR BCT RX BRANCH ON INDEX HIGH BRANCH ON INDEX LOW OR BXH RS BXLE RS EQUAL COMPARE COMPARE COMPARE AND SWAP CR C CS COMPARE DOUBLE AND SWAP CDS COMPAREHALFWORD CH COMPARE iLOGICAL CLR COMPARE iLOGICAL CL COMPARE iLOGICAL (character) CLC COMPARE !LOGICAL (immediate) CLI COMPARE !LOGICAL CHAR- CLM ACTERS UNDER MASK COMPARE LOGICAL LONG CONVERT TO BINARY CONVERT TO DECIMAL DIVIDE DIVIDE EXCLUSIVE OR EXCLUSIVE OR EXCLUSIVE OR (character) EXCLUSIVE OR (immediate) EXECUTE CLCL CVB CVD DR
D
XR
X XC XI EX INSERT CHARACTER IC INSERT CHARACTERS UNDER ICM MASK LOAD LOAD LOAD ADDRESS LOAD AND TEST LOAD COMPLEMENT LOAD HALFWORD LOAD MULTIPLE LOAD NEGATIVE LOAD POSITIVE MONITOR GALL MOVE (character)
LR
L
LA
LTR LCR LH
LM
LNR
LPR MC MVC General-Instruction Summary (Part 1 of 2)
118 System/370 Principles of Operation
RR C RX C RS C RS C RX C RR C ,.AX C SS C SI C RS C RR C RX
RX
RR
RX
RR C RX C SS C SI C RX
RX RS C RR
RX
RX
RR C RR C RX RS RR C RR C SI SS A
A
A
A
A
A
A SW A SW A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A SP SP SP SP SP SP SP Characteristics
D IF IF IF IF IF IK IK IK $ II EX MO B
B
B
B
B
B
B
B
R
R
R
R
R
R
R
R
R
R H R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R Code 1A
5A
4A
1E
5E
14
54 ST D4 ST 94 05 45 07 47 06 46
86
87
19
59 ST BA ST BB
49
15
55
D5
95
BD OF 4F ST 4E
1D
5D
17
57 ST D7 ST 97
44
43
BF
18
58
41
12
13
48
98
11 10 AF ST D2

Name Mnemonic Characteristics Code MOVE (immediate) MVI SI A ST 92 MOVE LONG MVCL RR C A SP II R ST OE MOVE NUMERICS MVN SS A ST D1 MOVE WITH OFFSET MVO SS A ST F1 MOVE ZONES MVZ SS A ST D3 MULTIPLY MR RR SP R 1C MULTIPLY M RX A SP R 5C MUL TIPL Y HALFWORD MH RX A R 4C OR OR RR C R
16 OR 0 RX C A R
56 OR (character) OC SS C A ST D6 OR (immediate) 01 SI C A ST 96
PACK PACK SS A ST F2 SET PROGRAM MASK SPM RR L 04 SHIFT LEFT DOUBLE SLDA RS C SP IF R
8F SHI FT LEFT DOUBLE LOGICAL SLDL RS SP R
8D SHIFT LEFT SINGLE SLA RS C IF R
8B SHIFT LEFT SINGLE LOGICAL SLL RS R
89 SHIFT RIGHT DOUBLE SRDA RS C SP R
8E SHIFT RIGHT DOUBLE LOGICAL SRDL RS SP R 8C SHIFT RIGHT SINGLE SRA RS C R
8A SHIFT RIGHTSINGLE LOGICAL SRL RS R
88 STORE ST RX A ST 50 STORE CHARACTER STC RX A ST 42 STORE CHARACTERS UNDER STCM RS A ST BE MASK STORE CLOCK STCK S C A $ ST B205 STORE HALFWORD STH RX A ST 40 STORE MULTIPLE STM RS A ST 90 SU8TRACT SR RR C IF R
18 SUBTRACT S RX C A IF R
58 SUBTRACTHALFWORD SH RX C A IF R
48 SUBTRACT LOGICAL SLR RR C R
1F SUBTRACT LOGICAL SL RX C A R
5F SUPERVISOR CALL SVC RR $ OA TEST AND SET TS S C A $ ST 93 TEST UNDER MASK TM SI C A 91
TRANSLATE TR SS A ST DC TRANSLATE AND TEST TRT SS C A R
DD
UNPACK UNPK SS A ST F3
Explanation:
A Access exceptions RS RS instruction format
8 PER branch event RX RX instruction format C Condition code is set S S instruction format
D
Data exception SI SI instruction format
EX Execute exception SP Specification exception IF Fixed-point-overflowexception SS SS instruction format II Interruptible instruction ST PER storage-alteration event IK Fixed-point-divide exception SW Conditional-swapping feature
L New condition code loaded $ Causes serialization MO Monitor event $1 Causes serialization when the R
1 and
R
PER general-register-alteration event R2 fields contain all ones and zeros, respectively
RR RR instruction format
General-Instruction Summary (Part 2 of 2)
General Instructions 119