Name Mnemonic Characteristics Code MOVE (immediate) MVI SI A ST 92 MOVE LONG MVCL RR C A SP II R ST OE MOVE NUMERICS MVN SS A ST D1 MOVE WITH OFFSET MVO SS A ST F1 MOVE ZONES MVZ SS A ST D3 MULTIPLY MR RR SP R 1C MULTIPLY M RX A SP R 5C MUL TIPL Y HALFWORD MH RX A R 4C OR OR RR C R
16 OR 0 RX C A R
56 OR (character) OC SS C A ST D6 OR (immediate) 01 SI C A ST 96
PACK PACK SS A ST F2 SET PROGRAM MASK SPM RR L 04 SHIFT LEFT DOUBLE SLDA RS C SP IF R
8F SHI FT LEFT DOUBLE LOGICAL SLDL RS SP R
8D SHIFT LEFT SINGLE SLA RS C IF R
8B SHIFT LEFT SINGLE LOGICAL SLL RS R
89 SHIFT RIGHT DOUBLE SRDA RS C SP R
8E SHIFT RIGHT DOUBLE LOGICAL SRDL RS SP R 8C SHIFT RIGHT SINGLE SRA RS C R
8A SHIFT RIGHTSINGLE LOGICAL SRL RS R
88 STORE ST RX A ST 50 STORE CHARACTER STC RX A ST 42 STORE CHARACTERS UNDER STCM RS A ST BE MASK STORE CLOCK STCK S C A $ ST B205 STORE HALFWORD STH RX A ST 40 STORE MULTIPLE STM RS A ST 90 SU8TRACT SR RR C IF R
18 SUBTRACT S RX C A IF R
58 SUBTRACTHALFWORD SH RX C A IF R
48 SUBTRACT LOGICAL SLR RR C R
1F SUBTRACT LOGICAL SL RX C A R
5F SUPERVISOR CALL SVC RR $ OA TEST AND SET TS S C A $ ST 93 TEST UNDER MASK TM SI C A 91
TRANSLATE TR SS A ST DC TRANSLATE AND TEST TRT SS C A R
DD
UNPACK UNPK SS A ST F3
Explanation:
A Access exceptions RS RS instruction format
8 PER branch event RX RX instruction format C Condition code is set S S instruction format
D
Data exception SI SI instruction format
EX Execute exception SP Specification exception IF Fixed-point-overflowexception SS SS instruction format II Interruptible instruction ST PER storage-alteration event IK Fixed-point-divide exception SW Conditional-swapping feature
L New condition code loaded $ Causes serialization MO Monitor event $1 Causes serialization when the R
1 and
R
PER general-register-alteration event R2 fields contain all ones and zeros, respectively
RR RR instruction format
General-Instruction Summary (Part 2 of 2)
General Instructions 119

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 Add Logical
[RR] L_1 E ----l-R-----L.-' I I o 8 12 15
J
D2 _____ o 8 12 16 20 31
The slecond operand is added to the first operand,
and the sum is placed in the first-operand location.
The occurrence of a carry out of the sign position is
recorded in the condition code.
Logical addition is performed by adding all 32
bits of both operands without further change to the
resulting sign bit. The instruction differs from ADD
in the meaning of the condition code and in the ab­
sence of the interruption for overflow.
If a carry out of the sign position occurs, the left­
most bit of the condition code is made one. In the absence of a carry, the bit is made zero. When the
sum is zero, the rightmost bit of the condition code is
made zero. For a nonzero sum, the bit is made one.
Resulting Condition Code:
o Sum is zero, with no carry
1 Sum is not zero, with no carry
2 Sum is zero, with carry
3 Sum is not zero, with carry
Progl'am Exceptions:
Access (fetch, operand 2 of AL only)
AN1)
NR Rl,R2 [RR] 120 System/370 Principles of Operation N R 1 ,D2(X2,B2) [RX] I 54 R, X
2 I B2 I 0 8 12 16 20 31
NI Dl(Bl),h [SI]
[
94 I 12 I B, I 0, I 0 8 16 20 31
NC [SS]
The AND of the first and second operands is placed
in the first-operand location. Operands are treated as unstructured logical
quantities, and the connective AND is applied bit by
bit. A bit position in the result is set to one if the
corresponding bit positions in both operands contain
a one; otherwise, the result bit is set to zero.
For NC, each operand field is processed left to
right. When the operands overlap, the result is ob­
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Resulting Condition Code:
o Result is zero
1 Result not zero
2 -
3 -
Program Exceptions:
Access (fetch, operand 2, Nand NC; fetch and
store, operand 1, NI and NC)
Programming Note
The instruction AND may be used to set a bit to
zero.
The execution of NI and NC consists in fetching a
first-operand byte from main storage and subse­
quently storing the updated value. These fetch and
store accesses to a particular byte do not necessarily
occur one immediately after the other. Thus, the
instruction AND cannot be safely used to update a
shared location in main storage if the possibility ex­
ists that another CPU or a channel may also be updat­
ing the location. For NI, only one byte is stored.