Branch and Link
BALR RI,R2 [RR]05 I R, I R2 I 0 8 12 15
BAL RI,D2(X2,B2) [RX]
45
I R, IX
2 I
B2 D20 8 12 16 20 31
Information from the currentPSW, including the
updated instruction address, is loaded as link infor
mation in the general register designated by RI. Subse
quently, the instruction address is replaced by the
branch address.
In the RX format, the second-operand address is
used as the brancha4dress. In the RR format, the
contents of bit positions 8-31 of the general register
designated by R2 are used as the branch address.
However, when the R2 field contains zeros, the op
eration is performed without branching.
The branch address is computed before the link
information is loaded. The link information, in both
the BC and EC modes, consists of the instruction
length code, the condition code, the program mask
bits, and the updated instruction address, arranged in
the following format:
Instruction AddressI 0 248 31
The instruction-length code is 1 or 2.
Condition Code:
The code remains unchanged.
Program Exceptions:
None When the R2 field in the RR format contains all
zeros, the link information is loaded without branch
ing. The format and the contents of the link infor
mation do not depend on whether thePSW specifies
the BC or EC mode.
When BRANCH AND LINK is the subject in
struction of EXECUTE, the instruction-length code
is 2.
In both the BC and EC modes, the link informa
tion is in the format of the rightmost 32 bit positions
of the BC-modePSW. Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Branch on Condition
BCR MI,R2 [RR]07 I M, I R2 I 0 8 12 15
BC MI,D2(X2,B2) [RX]I 47 I M, I X 2 I B2 D2 0 8 12 16 20 31
The updated instruction address in the currentPSW is replaced by the branch address if the state of the
condition code is as specified by MI; otherwise, nor
mal instruction sequencing proceeds with the updat
ed instruction address.I In the RX format the second-operand address is
used as the branch address. In the RR format the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address.
However, when the R2 field contains zeros, the oper
ation is performed without branching.
TheMI field is used as a four-bit mask. The four
bits of the mask correspond, left to right, with the
four condition codes(0, 1,2, and 3), as follows:
Instruction Bit Mask PositionValue Condition Code 8 8 0 9 4 1 10 2 2
11 3
The branch is successful whenever the condition
code has a corresponding mask bit of one.
When theMI and R2 fields of BCR are 15 and 0, respectively, a serialization function is performed. CPU operation is delayed until all previous storage
accesses by thisCPU to main storage have been
completed, as observed by channels and otherCPUs. No subsequent instructions or their operands
are· accessed by thisCPU until the execution of this
instructionis completed.
ConditionCode; The code remains unchanged.
Program Exceptions:
None When a branch is to be made on more than one con
dition code, the pertinent condition codes are speci
fied in the mask as the sum of their mask position
values. A mask of 12, for example, specifies that a
General Instructions 121
BALR RI,R2 [RR]
BAL RI,D2(X2,B2) [RX]
45
I R, I
2
B2 D2
Information from the current
updated instruction address, is loaded as link infor
mation in the general register designated by R
quently, the instruction address is replaced by the
branch address.
In the RX format, the second-operand address is
used as the branch
contents of bit positions 8-31 of the general register
designated by R2 are used as the branch address.
However, when the R2 field contains zeros, the op
eration is performed without branching.
The branch address is computed before the link
information is loaded. The link information, in both
the BC and EC modes, consists of the instruction
length code, the condition code, the program mask
bits, and the updated instruction address, arranged in
the following format:
Instruction Address
The instruction-length code is 1 or 2.
Condition Code:
The code remains unchanged.
Program Exceptions:
None
zeros, the link information is loaded without branch
ing. The format and the contents of the link infor
mation do not depend on whether the
the BC or EC mode.
When BRANCH AND LINK is the subject in
struction of EXECUTE, the instruction-length code
is 2.
In both the BC and EC modes, the link informa
tion is in the format of the rightmost 32 bit positions
of the BC-mode
By TNL: GN22-0498
Branch on Condition
BCR MI,R2 [RR]
BC MI,D2(X2,B2) [RX]
The updated instruction address in the current
condition code is as specified by MI; otherwise, nor
mal instruction sequencing proceeds with the updat
ed instruction address.
used as the branch address. In the RR format the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address.
However, when the R2 field contains zeros, the oper
ation is performed without branching.
The
bits of the mask correspond, left to right, with the
four condition codes
Instruction Bit Mask Position
11 3
The branch is successful whenever the condition
code has a corresponding mask bit of one.
When the
accesses by this
completed, as observed by channels and other
are· accessed by this
instruction
Condition
Program Exceptions:
None
dition code, the pertinent condition codes are speci
fied in the mask as the sum of their mask position
values. A mask of 12, for example, specifies that a
General Instructions 121