Branch and Link
BALR RI,R2 [RR] 05 I R, I R2 I 0 8 12 15
BAL RI,D2(X2,B2) [RX]
45
I R, I X
2
I
B2 D2 0 8 12 16 20 31
Information from the current PSW, including the
updated instruction address, is loaded as link infor­
mation in the general register designated by R I. Subse­
quently, the instruction address is replaced by the
branch address.
In the RX format, the second-operand address is
used as the branch a4dress. In the RR format, the
contents of bit positions 8-31 of the general register
designated by R2 are used as the branch address.
However, when the R2 field contains zeros, the op­
eration is performed without branching.
The branch address is computed before the link
information is loaded. The link information, in both
the BC and EC modes, consists of the instruction­
length code, the condition code, the program mask
bits, and the updated instruction address, arranged in
the following format:
Instruction Address I 0 248 31
The instruction-length code is 1 or 2.
Condition Code:
The code remains unchanged.
Program Exceptions:
None When the R2 field in the RR format contains all
zeros, the link information is loaded without branch­
ing. The format and the contents of the link infor­
mation do not depend on whether the PSW specifies
the BC or EC mode.
When BRANCH AND LINK is the subject in­
struction of EXECUTE, the instruction-length code
is 2.
In both the BC and EC modes, the link informa­
tion is in the format of the rightmost 32 bit positions
of the BC-mode PSW. Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Branch on Condition
BCR MI,R2 [RR] 07 I M, I R2 I 0 8 12 15
BC MI,D2(X2,B2) [RX] I 47 I M, I X 2 I B2 D2 0 8 12 16 20 31
The updated instruction address in the current PSW is replaced by the branch address if the state of the
condition code is as specified by MI; otherwise, nor­
mal instruction sequencing proceeds with the updat­
ed instruction address. I In the RX format the second-operand address is
used as the branch address. In the RR format the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address.
However, when the R2 field contains zeros, the oper­
ation is performed without branching.
The MI field is used as a four-bit mask. The four
bits of the mask correspond, left to right, with the
four condition codes (0, 1,2, and 3), as follows:
Instruction Bit Mask Position Value Condition Code 8 8 0 9 4 1 10 2 2
11 3
The branch is successful whenever the condition
code has a corresponding mask bit of one.
When the MI and R2 fields of BCR are 15 and 0, respectively, a serialization function is performed. CPU operation is delayed until all previous storage
accesses by this CPU to main storage have been
completed, as observed by channels and other CPUs. No subsequent instructions or their operands
are· accessed by this CPU until the execution of this
instruction is completed.
Condition Code; The code remains unchanged.
Program Exceptions:
None When a branch is to be made on more than one con­
dition code, the pertinent condition codes are speci­
fied in the mask as the sum of their mask position
values. A mask of 12, for example, specifies that a
General Instructions 121
branch is to be made on condition codes 0 and 1.
When all four mask bits are zero or when the R2
field in the RR format contains zero, the branch
instruetion is equivalent to no-operation" When all
four mask bits are ones, that is, the mask value is 15,
the branch is unconditional unless the R2 field in the
RR format is zero.
Execution of BCR 15,0 may result in significant
performance degradation, especially on larger mod­
els. To ensure optimum performance, the program
should avoid use of BCR 15,0 except in cases when
the seJrialization function is actually required.
Note that the relation between the RR and RX
formats in branch-address specification is not the
same as in operand-address specification. For branch instrw:!tions in the RX format, the branch address is
the address specified by X2, B2, and D2; in the RR
format, the branch address is in the low-order 24
bits of the register specified by R2. For operands,
the address specified by X2, B2, and D2 is the oper­
and address, but the register specified by R2 con­
tains the operand itself. Bran.ch on Count
BCTR Rl,R2 [RR] Los I R, I R2 I 0 8 12 15
BCT R 1 ,D2(X2,B2) [RX] L46 I R, I X
2 I 8
2 0 8 12 16 20 31
The contents of the general register specified by Rl
are algebraically reduced by one. When the result is
zero, normal instruction sequencing proceeds with
the updated instruction address. When the result is
not the instruction address in the current PSW
is replaced by the branch address.
In the RX format, the second-operand address is
used as the branch address. In the RR format, the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address. How­
ever, when the R2 field contains zeros, the operation
is performed without branching. branch address is computed before the count­
ing operation. Counting does not change the condi­
tion code. The overflow occurring on transition from
the maximum negative number to the maximum pos­
itive number is ignored. Otherwise, the subtraction as in fixed-point arithmetic, and all 32 bits
of the general register participate in the operation.
122 System/370 Principles of Operation Condition Code:
The code remains unchanged.
Program Exceptions:
None
Programming Notes
An initial count of one results in zero, and no
branching takes place; an initial count of zero results
in minus one and causes branching to be executed;
an initial count of minus one results in minus 2 and
causes branching to be executed; and so on. In a
loop, branching takes place each time the instruction
is executed until the result is again zero. Note that,
because of the number range, an initial count of
minus 231 results in the positive value of 231-1.
Counting is performed without branching when
the R2 field in the RR format contains zero.
Branch on Index High
BXH
86
o 8 12 16 20 31
An increment is added to the first operand, and the
sum is compared algebraically with a comparand.
Subsequently, the sum is placed in the first-operand
location, regardless of whether the branch is taken.
The second-operand address is used as the branch
address.
When the sum is high, the instruction address in
the current PSW is replaced by branch address.
When the sum is low or equal, instruction sequenc­
ing proceeds with the updated instruction address.
The first operand and the increment are in the
registers specified by Rl and R3. The comparand
register address is odd and is either one larger than
R3 or equal to R3. The branch address is computed
before the addition and comparison.
Overflow caused by the addition is ignored and
does not affect the comparison. Otherwise, the ad­
dition and comparison proceed as in fixed-point
arithmetic. All 32 bits of the general registers partici­
pate in the operations, and negative quantities are
expressed in two's-complement notation. When the
first operand and comparand locations coincide, the
original register contents are used. as the comparand.
Condition Code:
The code remains unchanged.
Program Exceptions:
None
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