branch is to be made on condition codes 0 and 1.
When all four mask bits are zero or when the R2
field in the RR format contains zero, the branch
instruetion is equivalent to no-operation" When all
four mask bits are ones, that is, the mask value is 15,
the branch is unconditional unless the R2 field in the
RR format is zero.
Execution of BCR15,0 may result in significant
performance degradation, especially on larger mod
els. To ensure optimum performance, the program
should avoid use of BCR15,0 except in cases when
the seJrialization function is actually required.
Note that the relation between the RR and RX
formats in branch-address specification is not the
sameas in operand-address specification. For branch instrw:!tions in the RX format, the branch address is
the address specified by X2, B2, and D2; in the RR
format, the branch address is in the low-order 24
bits of the register specified by R2. For operands,
the address specified by X2, B2, and D2 is the oper
and address, but the register specified by R2 con
tains the operand itself.Bran.ch on Count
BCTR Rl,R2 [RR]Los I R, I R2 I 0 8 12 15
BCT R 1 ,D2(X2,B2) [RX]L46 I R, I X
2I 8
20 8 12 16 20 31
The contents of the general register specified by Rl
are algebraically reduced by one. When the result is
zero, normal instruction sequencing proceeds with
the updated instruction address. When the result is
not the instruction address in the current PSW
is replaced by the branch address.
In the RX format, the second-operand address is
used as the branch address. In the RR format, the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address. How
ever, when the R2 field contains zeros,the operation
is performed without branching. branch address is computed before the count
ing operation. Counting does not change the condi
tion code. The overflow occurring on transition from
the maximum negative number to the maximum pos
itive number is ignored. Otherwise, the subtraction as in fixed-point arithmetic, and all 32 bits
of the general register participate in the operation.
122System/370 Principles of Operation Condition Code:
The code remains unchanged.
Program Exceptions:
None
Programming Notes
An initial count of one results in zero, and no
branching takes place; an initial count of zero results
in minus one and causes branching to be executed;
an initial count of minus one results in minus 2 and
causes branching to be executed; and so on. In a
loop, branching takes place each time the instruction
is executed until the result is again zero. Note that,
because of the number range, an initial count of
minus 231 results in the positive value of 231-1.
Counting is performed without branching when
the R2 field in the RR format contains zero.
Branch on Index High
BXH
86
o 8 12 1620 31
An increment is added to the first operand, and the
sum is compared algebraically with a comparand.
Subsequently, the sum is placed in the first-operand
location, regardless of whether the branch is taken.
The second-operand address is used as the branch
address.
When the sum is high, the instruction address in
the current PSW is replaced by branch address.
When the sum is low or equal, instruction sequenc
ing proceeds with the updated instruction address.
The first operand and the increment are in the
registers specified by Rl and R3. The comparand
register address is odd and is either one larger than
R3 or equal to R3. The branch address is computed
before the addition and comparison.
Overflow caused by the addition is ignored and
does not affect the comparison. Otherwise, the ad
dition and comparison proceed as in fixed-point
arithmetic. All 32 bits of the general registers partici
pate in the operations, and negative quantities are
expressed in two's-complement notation. When the
first operand and comparand locations coincide, the
original register contents are used. as the comparand.
Condition Code:
The code remains unchanged.
Program Exceptions:
None
When all four mask bits are zero or when the R2
field in the RR format contains zero, the branch
instruetion is equivalent to
four mask bits are ones, that is, the mask value is 15,
the branch is unconditional unless the R2 field in the
RR format is zero.
Execution of BCR
performance degradation, especially on larger mod
els. To ensure optimum performance, the program
should avoid use of BCR
the seJrialization function is actually required.
Note that the relation between the RR and RX
formats in branch-address specification is not the
same
the address specified by X2, B2, and D2; in the RR
format, the branch address is in the low-order 24
bits of the register specified by R2. For operands,
the address specified by X2, B2, and D2 is the oper
and address, but the register specified by R2 con
tains the operand itself.
BCTR Rl,R2 [RR]
BCT R 1 ,D2(X2,B2) [RX]
2
2
The contents of the general register specified by Rl
are algebraically reduced by one. When the result is
zero, normal instruction sequencing proceeds with
the updated instruction address. When the result is
not
is replaced by the branch address.
In the RX format, the second-operand address is
used as the branch address. In the RR format, the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address. How
ever, when the R2 field contains zeros,
is performed without branching.
ing operation. Counting does not change the condi
tion code. The overflow occurring on transition from
the maximum negative number to the maximum pos
itive number is ignored. Otherwise, the subtraction
of the general register participate in the operation.
122
The code remains unchanged.
Program Exceptions:
None
Programming Notes
An initial count of one results in zero, and no
branching takes place; an initial count of zero results
in minus one and causes branching to be executed;
an initial count of minus one results in minus 2 and
causes branching to be executed; and so on. In a
loop, branching takes place each time the instruction
is executed until the result is again zero. Note that,
because of the number range, an initial count of
minus 231 results in the positive value of 231-1.
Counting is performed without branching when
the R2 field in the RR format contains zero.
Branch on Index High
BXH
86
o 8 12 16
An increment is added to the first operand, and the
sum is compared algebraically with a comparand.
Subsequently, the sum is placed in the first-operand
location, regardless of whether the branch is taken.
The second-operand address is used as the branch
address.
When the sum is high, the instruction address in
the current PSW is replaced by
When the sum is low or equal, instruction sequenc
ing proceeds with the updated instruction address.
The first operand and the increment are in the
registers specified by Rl and R3. The comparand
register address is odd and is either one larger than
R3 or equal to R3. The branch address is computed
before the addition and comparison.
Overflow caused by the addition is ignored and
does not affect the comparison. Otherwise, the ad
dition and comparison proceed as in fixed-point
arithmetic. All 32 bits of the general registers partici
pate in the operations, and negative quantities are
expressed in two's-complement notation. When the
first operand and comparand locations coincide, the
original register contents are used. as the comparand.
Condition Code:
The code remains unchanged.
Program Exceptions:
None