Resulting Condition Code:
o First and second operands equal, second oper­ and replaced by third operand
1 First and second operands unequal, first oper­
and replaced by second operand
2 -
3 - Program Exceptions:
Operation (if the conditional-swapping feature is
not installed) Specification Access (fetch and store, operand 2)
Programming Notes
The instruction COMPARE AND SWAP ean be
used by programs sharing common storage areas in
either a multiprogramming or multiprocessing envi­
ronment. The following are two examples:
By performing the following procedure, a pro­
gram can modify the contents of a storage location
even though the possibility exists that the program
may be interrupted by another program that will
update the location or even though the possibility
exists that another CPU may simultaneously update
the location. First, the entire word containing the
byte or bytes to be updated is loaded into a general
register. Next, the updated value is computed and
placed in another general register. Then the instruc­
tion AND SWAP is executed with the
Rl field designating the register that contains the
original value and the R3 field designating the regis­
ter that contains the updated value. If condition code
o is set, the update has been successful. If condition
code 1 is set, the storage location no longer contains
the original value, the update has not been success­
ful, and the general register designated by the Rl
field of the COMPARE AND SWAP instruction
contains the new current value of the storage loca­
tion. When condition code 1 is set, the program can
repeat the procedure using the new current value. COMPARE AND SWAP may be used for con­
trolled sharing of a common storage area in a man­
ner similar to that described in the programming
note unde:r TEST AND SET, but it provides the
added capability of leaving a message when the com­
mon area is in use. To accomplish this, a word in
storage may be used as a control word, with a zero
value in the word indicating that the common area is
not in use, a negative value indicating that the area is
in use, and a nonzero positive value indicating that
the common area is in use and that the value is the
address of the most recent message added to the list.
Thus, any number of programs desiring to seize the
124 System/370 Principles of Operation area may use COMPARE AND SWAP to update
the control word to indicate that the area is in use or
to add messages to the list. The single program
which has seized the area may also safely use COM­ P ARE AND SW AP to remove messages from the
list.
It should be noted that COMPARE AND SWAP does not interlock against storage accesses by chan­
nels. Therefore, the instruction should not be used to
update a word, all or part of which is in an 110 input
area, since the input data may be lost.
Compare Double and Swap
CDS [RS]
BB
o 8 12 16 20 31
The first and second operands are compared. If they
are equal, the third operand is stored in the second­
operand location. If they are unequal, the second
operand is loaded into the first-operand location.
The first and third operands are 64 bits in length,
with each operand occupying an even-odd pair of
general registers. The second operand is a double­
word in main storage.
The result of the 64-bit comparison, either equal
or unequal, is used to set the condition code. When
the result of the comparison is unequal, no attempt
to store occurs, and no change-bit and store-
protection actions are taken. .
When an equal comparison occurs, no access by
another CPU is permitted at the second-operand
location between the moment that the second oper­
and is fetched for comparison and the moment that
the third operand is stored at the second-operand
location.
A serialization function is performed before the
operand is fetched, and, if condition code 0 is set,
after the result is stored. CPU operation is delayed
until all previous accesses by this CPU to main stor­
age have been completed, as observed by channels
and other CPUs, and then the second operand is
fetched. No subsequent instructions or their oper­
ands are accessed by this CPU until the instruction
is completed, including placing the result value, if
any, in main storage, as observed by channels and
other CPUs. The R 1 and R3 fields must each designate an even
register, and the second operand must be designated <,?n a double word boundary; otherwise, a specific a­ tiOiiexceptiolfis recogniied;--arid"lhe operation is
suppressed.

Resulting Condition Code:
o First and second operands equal, second oper -
and replaced by third operand
1 First and second operands not equal, first oper -
and replaced by second operand
2 -
3 -
Program Exceptions:
Operation (if the conditional-swapping feature is
not installed)
Specification
Access (fetch and store, operand 2)
Programming Note
The instruction COMPARE DOUBLE AND
SW AP may be used in a manner similar to that de­
scribed in the programming notes for COMPARE AND SWAP. In addition, it has another use. Consider a chained
list, with a control word used to address the first
message in the list, as described in the second exam­
ple for COMPARE AND SWAP. If mUltiple pro­
grams are permitted to add and delete messages by
using COMPARE AND SWAP, there is a possibility
the list will be incorrectly updated. This would occur
if, after one program has fetched the address of the
most recent message in order to remove the message,
another program removes the first two messages and
then adds the first message back into the chain. The
first program, on continuing, is not aware that the
list is changed. By increasing the size of the control
word to a double word containing both the first mes­
sage address and a word with a change number that
is incremented for each modification of the list, and
by using COMPARE DOUBLE AND SWAP to
update both fields together, the possibility of the list
being incorrectly updated is reduced to a negligible
level. That is, an incorrect update can occur only
if the first program is delayed while changes exact\y equal in number to a mUltiple of 2
32
'take place
and only if the last change places the original message
address in the control word.
It should be noted that COMPARE DOUBLE AND SW AP does not interlock against storage ac­
cesses by channels. Therefore, the instruction should
not be used to update a double word all or part of
which is in an 110 input area, since the input data
may be lost.
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Compare Hal/word
CH
o 8 12 16 20 31
The first operand is compared with the second oper­ and, and the result determines the setting of the
condition code. The second operand is two bytes in
length and is considered to be a 16-bit signed inte­
ger.
The second operand is expanded to 32 bits before
the comparison by propagating the sign-bit value
through the 16 high-order bit positions.
Comparison is algebraic, treating both compa­
rands as 32-bit signed integers. Operands in regis­
ters or storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 -
Program Exceptions:
Access (fetch, operand 2)
Compare Logif;al CLR Rl,R2 [RRJ
15 I R, I R2 I 0 8 12 15
CL R 1 ,D2(X2,B2)
55 I R, I X
2
[RX]
8
2 °2 I 0 8 12 16 20 31
CLI Dl(Bl),h [SI] I 95 12 I 6, I °1 0 8 16 20 31
CLC Dl(L,Bl),D2(B2) [8S] 05 L 8
1 lSI 8
2 I 0 8 16 20 32 36 47
General Instructions 125