Resulting Condition Code:
o First and second operands equal, second oper -
and replaced by third operand
1 First and second operands not equal, first oper -
and replaced by second operand
2 -
3 -
Program Exceptions:
Operation (if the conditional-swapping feature is
not installed)
Specification
Access (fetch and store, operand 2)
Programming Note
The instruction COMPARE DOUBLE AND
SW AP may be used in a manner similar to that de­
scribed in the programming notes for COMPARE AND SWAP. In addition, it has another use. Consider a chained
list, with a control word used to address the first
message in the list, as described in the second exam­
ple for COMPARE AND SWAP. If mUltiple pro­
grams are permitted to add and delete messages by
using COMPARE AND SWAP, there is a possibility
the list will be incorrectly updated. This would occur
if, after one program has fetched the address of the
most recent message in order to remove the message,
another program removes the first two messages and
then adds the first message back into the chain. The
first program, on continuing, is not aware that the
list is changed. By increasing the size of the control
word to a double word containing both the first mes­
sage address and a word with a change number that
is incremented for each modification of the list, and
by using COMPARE DOUBLE AND SWAP to
update both fields together, the possibility of the list
being incorrectly updated is reduced to a negligible
level. That is, an incorrect update can occur only
if the first program is delayed while changes exact\y equal in number to a mUltiple of 2
32
'take place
and only if the last change places the original message
address in the control word.
It should be noted that COMPARE DOUBLE AND SW AP does not interlock against storage ac­
cesses by channels. Therefore, the instruction should
not be used to update a double word all or part of
which is in an 110 input area, since the input data
may be lost.
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Compare Hal/word
CH
o 8 12 16 20 31
The first operand is compared with the second oper­ and, and the result determines the setting of the
condition code. The second operand is two bytes in
length and is considered to be a 16-bit signed inte­
ger.
The second operand is expanded to 32 bits before
the comparison by propagating the sign-bit value
through the 16 high-order bit positions.
Comparison is algebraic, treating both compa­
rands as 32-bit signed integers. Operands in regis­
ters or storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 -
Program Exceptions:
Access (fetch, operand 2)
Compare Logif;al CLR Rl,R2 [RRJ
15 I R, I R2 I 0 8 12 15
CL R 1 ,D2(X2,B2)
55 I R, I X
2
[RX]
8
2 °2 I 0 8 12 16 20 31
CLI Dl(Bl),h [SI] I 95 12 I 6, I °1 0 8 16 20 31
CLC Dl(L,Bl),D2(B2) [8S] 05 L 8
1 lSI 8
2 I 0 8 16 20 32 36 47
General Instructions 125
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 The first operand is compared with the seeond oper­
and, and the result is indicated in the condition
code. The comparison is performed with the operands
considered as binary unsigned quantities, with all
codes valid. The operation proceeds left to right and
ends as soon as an inequality is found or an end of
the fields is reached.
When part of an operand in CL or CLC is desig­
nated in an inaccessible location but the operation
can be completed by using the accessible operand
parts, it is unpredictable whether the access excep­
tion for the inaccessible part is recognized.
Resulting Condition Code:
o Operands are equal
1 First operand is ,low 2 First operand is high
3 - Program Exceptions: Aecess (fetch, operand 2, CL and CLC; fetch,
operand 1, CLI and CLC) Programming Note
The COMPARE LOGICAL instruction treats all
bits alike as part of an unsigned binary quantity. In
variable-length operation, comparison may extend to
field lengths of 256 bytes. The operation may be
used to compare unsigned packed decimal fields or
alphameric information in any code that has a collat­
ing slequence based on ascending or descending bi­
nary values. For example, EBCDIC has a collating sequence based on ascending binary values. COJ'IIpare Logical Characters Under Mask
The second operand is compared with the first oper'- and, under control of a mask, and the result is indi­
cated in the condition code.
The contents of the M3 field, bit positions 12-15,
are used as a mask. The four bits of the mask, left to
right, correspond one for one with the four bytes,
left to right, of the general register designated by the
R 1 field. The byte positions corresponding to ones in
the mask are considered as a contiguous field and
126 System/370 Principles of Operation
are compared with the second operand. The second
operand is a contiguous field in storage, starting at
the second-operand address and equal in length to
the number of ones in the mask. The bytes in the
general register corresponding to zeros in the mask
do not participate in the operation.
The comparison is performed with the operands
considered as binary unsigned quantities, with all
codes valid. The operation proceeds left to right.
When the mask is not zero, exceptions associated
with storage-operand access are recognized only for
the number of bytes specified by the mask. Howev­
er, when part of the designated storage operand is in
an inaccessible location but the operation can be
completed by using the accessible operand parts, it is
unpredictable whether the exception for the inaccess­
ible part is indicated. When the mask is zero, access
exceptions are recognized for one byte. Resulti,:" Condition Code:
o Selected bytes are equal, or mask is zero
1 Selected field of first operand is low
2 Selected field of first operand is high
3 -
Program Exceptions:
Access (fetch, operand 2)
Compare Logical Long
CLCL Rl,R2 [RR] OF o
The first operand is compared with the second oper­
and, and the result is indicated in the condition
code. The shorter operand is considered extended
with the padding character.
The Rl and R2 fields each specify an even-odd
pair of general registers and must designate an even­
numbered register; otherwise, a specification excep­
tion is recognized.
The location of the leftmost byte of the first oper­
and and second operand is designated by bits 8-31
of the general registers specified by the Rl and R2
fields, respectively. The number of bytes in the first­
operand and second-operand locations is specified
by bits 8-31 of the general registers having addresses
Rl + 1 and R2+ 1, respectively. Bit positions 0-7 of
register R2 + 1 contain the padding character. The
contents 01" bit positions 0-7 of registers Rl, R2, and
R 1 + 1 are ignored.
Graphically, the contents of the registers just de­
scribed are as follows:
Previous Page Next Page