R1 First-Operand Address I 0 8 31
R1 + 1 First-Operand Length 0 8
31
R2 Second-Operand Address 0 8 31
R2 + 1 I Pad Second-Operand Length 0 8 31
The comparison is performed with the operands
considered as binary unsigned quantities, with all
codes valid. The comparison starts at the high-order
end of both fields and proceeds to the right. The
operation ends as soon as an inequality is detected
or the end of the longer operand is reached. If the
operands are not of the same length, the shorter
operand is extended, for the purpose of comparison,
with the padding character.
If both operands are of zero length, the operands
are considered equal.
The execution of the instruction is interruptible.
When an interruption occurs after a unit of opera­
tion other than the last one, the contents of registers
R 1 + 1 and R2 + 1 are decremented by the number of
bytes compared, and the contents of registers Rl and
R2 are incremented by the same number, so that the
instruction, when re-executed, resumes at the point
of interruption. The high-order byte of registers Rl
and R2 is set to zero; the contents of the high-order
byte of registers Rl + 1 and R2+ 1 remain un­
changed; and the condition code is unpredictable. If
the operation is interrupted after the shorter operand
has been exhausted, the count field pertaining to the
shorter operand is zero, and its address is updated
accordingly.
If the operation ends' because of a mismatch, the
count and address fields at completion identify the
byte of mismatch. The contents of bit positions
8-31 of registers Rl + 1 and R2+ 1 are decremented
by the number of bytes that matched, unless the
mismatch occurred with the padding character, in
which case the count field for the shorter operand is
set to zero. The contents of bit positions 8-31 of
registers Rl and R2 are incremented by the ap:lounts by which the corresponding count fields were re­
duced. If the two operands, including the padding
character, if necessary, are equal, both count fields
are made zero at completion, and the addresses are
incremented by the corresponding count values. The
contents of bit positions 0-7 of registers Rl and R2
are set to zero, including the case when one or both
of the original count values are zero. The contents of
bit positions 0-7 of registers R 1 + 1 and R2 + 1 remain
unchanged.
When part of an operand is designated in an inac­
cessible location, but the operation can be completed
by using the available operand parts, it is unpredicta­
ble whether the access exception for the inaccessible
part is recognized.
When the count field for an operand has the value
zero, no access exceptions are recognized for that
operand.
Resulting Condition Code:
o Operands are equal, or both fields have zero
length
1 First operand is low
2 First operand is high
3 -
Program Exceptions:
Access (fetch, operands 1 and 2)
Specification
Programming Notes
When the contents of the R 1 and R2 fields are the
same, condition code 0 is set, and protection and
addressing exceptions are indicated when called for
by the operand designation. Special precautions should be taken when COM­ P ARE LOGICAL LONG is made the subject of
EXECUTE. See the programming notes under EX­
ECUTE. See also the programming notes under MOVE LONG.
Convert to Binary CVB [RX]
4F
o 8 12 16 20 The radix of the second operand is changed from
decimal to binary, and the result is placed in the
first-operand location. The number is treated as a
right-aligned signed integer both before and after
conversion.
31
The second operand has the packed decimal data
format and is checked for valid sign and digit codes.
Improper codes are a data exception and cause a
General Instructions 127

program interruption. The decimal operand occupies
eight bytes in storage. The low-order four bits of the
field represent the sign. The remaining 60 bits con­
tain 15 binary-coded-decimal digits in true notation.
The packed decimal data format is described under
"Decimall Instructions."
The result of the conversion is placed in the gen­
eral register specified by Rt. The maximum number
that can be converted and still be contained in a
32-bit register is 2,147,483,647; the minimum num­
ber is -2,147,483,648. For any decimal number out­
side this range, the operation is completed by placing
the 32 low-order binary bits in the register; a fixed­
point divide exception exists, and a program inter­
ruption follows. In the case of a negative second
operand, the low-order part is in two's-complement
notation.
Conditioll' Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Data
Fixed-Point Divide
Converlr to Decimal CVD o 8 12 16
[RX] 20 31
The radix of the first operand is changed from bina­
ry to decimal, and the result is stored in the second­
operand location. The number is treated as a right­
aligned signed integer both before and after conver­
sion.
The result is placed in the storage location desig­
nated by the second operand and has the packed
decimal format, as described in "Decimal Instruc­
tions." The result occupies eight bytes in storage.
The low-order four bits of the field represent the
sign. A positive sign is encoded as 1100; a negative
sign is eneoded as 1101. The remaining 60 bits con­
tain 15 binary-coded-decimal digits in true notation.
The number to be converted is obtained as a 32-
bit signed integer from a general register. Since 15
decimal digits are available for the decimal equiva­
lent of 31 bits, an overflow cannot occur.
Condition Code:
The code remains unchanged.
128 System/370 Principles of Operation Program Exceptions: ,Access (store, operand 2)
Divide
DR Rt,R2 [RR]
10 R1 I R2 I 0 8 12 15
D R t ,D2(X2,B2) [RX]
50 I R, I X
2 I B2 0 8 12 16 I O
2 I 20 31
The dividend (first operand) is divided by the divisor
(second operand) and replaced by the remainder and
the quotient.
The dividend is a 64-bit signed integer and occu­
pies the even-odd pair of registers specified by the
Rt field of the instruction. A specification exception
occurs when Rt is odd. A 32-bit signed remainder
and a 32-bit signed quotient replace the dividend in
the even-numbered and odd-numbered registers,
respectively. The divisor is a 32-bit signed integer.
The sign of the quotient is determined by the
rules of algebra. The remainder has the same sign as
the dividend, except that a zero quotient or a zero
remainder is always positive. When the relative mag­
nitude of dividend and divisor is such that the quo­
tient cannot be expressed by a 32-bit signed integer,
a fixed-point divide exception is recognized (a pro­
gram interruption occurs, no division takes place,
and the dividend remains unchanged in the general
registers).
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of D only)
Specification
Fixed-Point Divide
Exclusive OR XR [RR]
17
o 8 12 15