Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Load lMultiple LM [R8]
The set of general registers starting with the register
specified by Rl and ending with the register speci­
fied by R3 is loaded from the locations designated by
the second-operand address.
The storage area from which the contents of the
general registers are obtained starts at the location
designated by the second-operand address and con­
tinues through as many locations as needed. The
general registers are loaded in the ascending order of
their addresses, starting with the register specified by
R 1 and (;ontinuing up to and including the register
specified by R3, with register 0 following register 15.
Conditi(Jln Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Programming Note
All combinations of register addresses specified by
R
1 and H .. 3 are valid. When the register addresses are
equal, only one word is transmitted. When the ad­
dress specified by R3 is less than the address speci­
fied by Rl, the register addresses wrap around from
15 to O. Load lVegative
LNR [RR]
The two's complement of the absolute value of the
second operand is placed in the first-operand loca­
tion.
The openition complements positive numbers;
negative numbers remain unchanged. The number
zero remains unchanged with positive sign.
132 System/370 Principles of Operation Resulting Condition Code: o Result is zero
1 Result is less than zero
2 -
3 -
Program Exceptions: None.
Load Positive
[RR] 10 o 8 12 15
The absolute value of the second operand is placed
in the first-operand location.
The operation includes complementation of nega­
tive numbers; positive numbers remain unchanged.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code: o Result is zero
1 -
2 Result is greater than zero
3 Overflow Program Exceptions:
Fixed-Point Overflow Monitor Call
[81]
AF 12 o 8 16
8, D, 20 A program interruption is caused if the appropriate
monitor-mask bit in control register 8 is one.
31
Bit positions 12-15 in the h field contain a binary
number specifying one of 16 monitoring classes.
When the monitor-mask bit corresponding to the
class specified by the h field is one, a program inter­
ruption for monitoring occurs. The contents of the h field are stored at location 149 of main storage, with
zeros stored at location 148. Bit 9 of the program
interruption code is set to one.
The address specified by the Bl and Dl fields
forms the monitor code, which is placed at locations
157-159. Address computation follows the rules of
address arithmetic. The address is not inspected for
access exceptions. Zeros are stored at location 156.
When the monitor-mask bit corresponding to the
class specified by bits 12-15 of the instruction is
zero, no interruption occurs, and the instruction is
executed as a no-operation.
Bit positions 8-11 of the instruction must contain
zeros; otherwise, a specification exception is recog­
nized, and the operation is suppressed.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Monitoring
Programming Notes
The monitoring function is useful in performing vari­
ous measurement functions; specifically, by implant­
ing MONITOR CALL instructions within the code,
tracing information can be generated indicating
which programs were executed, counting informa­
tion can be generated indicating how often particular
programs are used, and timing information can be
generated indicating how long a particular program
required for execution.
The monitor code provides a means of associating
descriptive information, in addition to the class num­
ber, with each MONITOR CALL instruction. With­
out the use of a base register, up to 4,096 distinct
monitor codes can be associated with a monitoring
interruption. With the base register designated by a
nonzero value in the Bt field, each monitoring inter­
ruption can be identified by a 24-bit code.
The monitor masks provide a means of disallow­
ing all interruptions due to MONITOR CALL or
allowing monitoring for all or selected classes.
Move
MVI Dt(Bt),Iz lSI] 92 I 12 B, 0, 0 8 16 20 31
MVC Dt(L,Bt),D2(B2) [SS] 02 L B, I 8
2 I 0 8 16 20 32 36 47
The second operand is placed in the first-operand
location.
Page of GA22-70004 Revised September 1, 1975
By TNL: GN22-0498
For MVC, each operand field is processed left to
right. When the operands overlap, the result is ob­
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of MVC; store, operand
1, MVI and MVC)
Programming Note
It is possible to propagate one character through an
entire field by having the first-operand field start
one character to the right of the second-operand
field.
Move Long
MVCL [RR]
o 8 12 15
The second operand is placed in the first-operand
location, provided overlapping of operand locations
does not affect the final contents of the first­
operand location. The remaining low-order byte
positions, if any, of the first-operand location are
filled with the padding character.
The Rt and R2 fields each specify an even-odd
pair of general registers and must designate an even­
numbered register; otherwise, a specification excep­
tion is recognized.
The location of the leftmost byte of the first oper­
and and second operand is designated by bits 8-31
of the general registers specified by the Rt and R2
fields, respectively. The number of bytes in the first­
operand and second-operand locations is specified
by bits 8-31 of general registers having addresses
R t + 1 and R2 + 1, respectively. Bit positions 0-7 of
register R2 + 1 contain the padding character. The
contents of bit positions 0-7 of registers R t, R2, and
R t + 1 are ignored.
Graphically, the contents of the registers just de­
scribed are as follows:
F irst-Operand Address
o 8 31
General Instructions 133
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