Programming Notes
The ORing of eight bits from the general register
with the designated instruction permits indirect
length, index, mask, immediate data, and arithmetic­
register specification.
If the subject instruction is a successful branch,
the length code still stands at 2.
An addressing or specification exception may be
caused by EXECUTE or by the subject instruction.
When an interruptible instruction is made a sub­
ject of EXECUTE, the program normally should not
designate any register updated by the interruptible
instruction as either the Rl, X2, or B2 register for EXECUTE, since on resumption of execution after
an interruption, or if the instruction is refetched
without an interruption, the updated values of these
registers will be used in the execution of EXECUTE.
Similarly, the program should normally not let the
destination field of an interruptible instruction in­
clude the location of the EXECUTE, since the new
contents of the location may be interpreted for a
resumption of the execution.
Insert Character
[RX]
The byte at the second-operand location is inserted
into bit positions 24-31 of the general register desig­
nated by the Rl field. The remaining bits in the reg­
ister remain unchanged. ContJ'ition COde: The code remains unchanged. Exceptions: Aecess (fetch, operand 2)
Inse'rt Characters Under Mask
Bytes from contiguous locations beginning at the
second-operand address are inserted into the first­ operand location under control of a mask.
31 The contents of the M3 field, bit positions 12-15,
are used as a mask. The four bits of the mask, left to
right, correspond one for one with the four bytes, 130 System/370 Principles of Operation left to right, of the general register designated by the
Rl field. The byte positions corresponding to ones in
the mask are filled, in the order of ascending byte
numbers, with bytes from the storage operand. Bytes
are fetched from contiguous storage locations begin­
ning at the second-operand address. The length of
the second operand is equal to the number of ones in
the mask. The bytes in the general register corre­
sponding to zeros in the mask remain unchanged.
The resulting condition code is based on the mask
and on the value of the bits inserted. When the mask
is zero or when all inserted bits are zero, the condi­
tion code is made O. When all inserted bits are not
zero, the code is set according to the leftmost bit of
the storage operand: if this bit is one, the code is
made 1 to indicate a negative algebraic value; if this
bit is zero, the code is made 2, reflecting a positive
algebraic value.
When the mask is not zero, exceptions associated
with storage operand access are recognized only for
the number of bytes specified by the mask. When
the mask is zero, access exceptions are recognized
for one byte.
Resulting Condition Code:
o All inserted bits are zeros, or mask is zero
1 First bit of the inserted field is one
2 First bit of the inserted field is zero, and not all
inserted bits are zeros
3 -
Program Exceptions:
Access (fetch, operand 2)
Programming Note
The condition code for INSERT CHARACTERS
UNDER MASK is defined such that when the mask
is 1111, the instruction causes the same condition
code to be set as for LOAD AND TEST.
Load
[RR]
o 8 12 15
L [RX]
58
o 8 12 16 20 31
The second operand is placed unchanged in the first­
operand location.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of L only)
Load Address
[RX]
41
o 8 12 16 20 31
The address specified by the X2, B2, and D2 fields is
inserted in bit positions 8-31 of the general register
specified by the R 1 field. Bits 0-7 of the register are
set to zeros. The address computation follows the
rules for address arithmetic.
No storage references for operands take place,
and the address is not inspected for access excep­
tions.
Condition Code:
The code remains unchanged.
Program Exceptions:
None.
Programming Note
The same general register may be specified by the
R 1, X2, and B2 instruction field, except that general
register 0 can be specified only by the Rl field. In
this manner it is possible to increment the low-order
24 bits of a general register, other than 0, by the
contents of the D2 field of the instruction. The regis­
ter to be incremented should be specified by Rl and
by either X2 (with B2 set to zero) or B2 (with X2 set
to zero).
Load and Test
LTR Rl,R2 [RR]
12
o 8 12 15
The second operand is placed unchanged in the first­
operand location, and the sign and magnitude of the
second operand determine the condition code.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
None.
Programming Note
When the Rl and R2 fields designate the same regis­
ter, the operation is equivalent to a test without data
movement.
Load Complement
LCR [RR]
o 8 12 15
The two's complement of the second operand is
placed in the first-operand location.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Program Exceptions:
Fixed-Point Overflow
Programming Note
Zero remains unchanged by complementation.
Load Hal/word
LH [RX]
48
o 8 12 16 20 31
The second operand is placed in the first-operand
location. The second operand is two bytes in length
and is considered to be a 16-bit signed integer.
The second operand is expanded to 32 bits by
propagating the sign-bit value through the 16 high­
order bit positions. Expansion occurs after the oper­
and is obtained from storage and before insertion in
the register.
General Instructions 131
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