157-159. Address computation follows the rules of
address arithmetic. The address is not inspected for
access exceptions. Zeros are stored at location 156.
When the monitor-mask bit corresponding to the
class specified by bits 12-15 of the instruction is
zero, no interruption occurs, and the instruction is
executed as a no-operation.
Bit positions 8-11 of the instruction must contain
zeros; otherwise, a specification exception is recog
nized, and the operation is suppressed.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Monitoring
Programming Notes
The monitoring function is useful in performing vari
ous measurement functions; specifically, by implant
ingMONITOR CALL instructions within the code,
tracing information can be generated indicating
which programs were executed, counting informa
tion can be generated indicating how often particular
programs are used, and timing information can be
generated indicating how long a particular program
required for execution.
The monitor code provides a means of associating
descriptive information, in addition to the class num
ber, with eachMONITOR CALL instruction. With
out the use of a base register, up to4,096 distinct
monitor codes can be associated with a monitoring
interruption. With the base register designated by a
nonzero value in the Bt field, each monitoring inter
ruption can be identified by a 24-bit code.
The monitor masks provide a means of disallow
ing all interruptions due toMONITOR CALL or
allowing monitoring for all or selected classes.
Move
MVIDt(Bt),Iz lSI] 92 I 12 B, 0, 0 8 16 20 31
MVC Dt(L,Bt),D2(B2)[SS] 02 L B, I 8
2I 0 8 16 20 32 36 47
The second operand is placed in the first-operand
location.
Page ofGA22-70004 Revised September 1, 1975
By TNL: GN22-0498
For MVC, each operand field is processed left to
right. When the operands overlap, the result is ob
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of MVC; store, operand
1, MVI and MVC)
Programming Note
It is possible to propagate one character through an
entire field by having the first-operand field start
one character to the right of the second-operand
field.
Move Long
MVCL [RR]
o 8 12 15
The second operand is placed in the first-operand
location, provided overlapping of operand locations
does not affect the final contents of the first
operand location. The remaining low-order byte
positions, if any, of the first-operand location are
filled with the padding character.
The Rt and R2 fields each specify an even-odd
pair of general registers and must designate an even
numbered register; otherwise, a specification excep
tion is recognized.
The location of the leftmost byte of the first oper
and and second operand is designated by bits 8-31
of the general registers specified by the Rt and R2
fields, respectively. The number of bytes in the first
operand and second-operand locations is specified
by bits 8-31 of general registers having addresses
R t + 1 and R2 + 1, respectively. Bit positions0-7 of
register R2 + 1 contain the padding character. The
contents of bit positions0-7 of registers R t, R2, and
R t + 1 are ignored.
Graphically, the contents of the registers just de
scribed are as follows:
F irst-Operand Address
o 8 31
General Instructions 133
address arithmetic. The address is not inspected for
access exceptions. Zeros are stored at location 156.
When the monitor-mask bit corresponding to the
class specified by bits 12-15 of the instruction is
zero, no interruption occurs, and the instruction is
executed as a no-operation.
Bit positions 8-11 of the instruction must contain
zeros; otherwise, a specification exception is recog
nized, and the operation is suppressed.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Monitoring
Programming Notes
The monitoring function is useful in performing vari
ous measurement functions; specifically, by implant
ing
tracing information can be generated indicating
which programs were executed, counting informa
tion can be generated indicating how often particular
programs are used, and timing information can be
generated indicating how long a particular program
required for execution.
The monitor code provides a means of associating
descriptive information, in addition to the class num
ber, with each
out the use of a base register, up to
monitor codes can be associated with a monitoring
interruption. With the base register designated by a
nonzero value in the Bt field, each monitoring inter
ruption can be identified by a 24-bit code.
The monitor masks provide a means of disallow
ing all interruptions due to
allowing monitoring for all or selected classes.
Move
MVI
MVC Dt(L,Bt),D2(B2)
2
The second operand is placed in the first-operand
location.
Page of
By TNL: GN22-0498
For MVC, each operand field is processed left to
right. When the operands overlap, the result is ob
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of MVC; store, operand
1, MVI and MVC)
Programming Note
It is possible to propagate one character through an
entire field by having the first-operand field start
one character to the right of the second-operand
field.
Move Long
MVCL [RR]
o 8 12 15
The second operand is placed in the first-operand
location, provided overlapping of operand locations
does not affect the final contents of the first
operand location. The remaining low-order byte
positions, if any, of the first-operand location are
filled with the padding character.
The Rt and R2 fields each specify an even-odd
pair of general registers and must designate an even
numbered register; otherwise, a specification excep
tion is recognized.
The location of the leftmost byte of the first oper
and and second operand is designated by bits 8-31
of the general registers specified by the Rt and R2
fields, respectively. The number of bytes in the first
operand and second-operand locations is specified
by bits 8-31 of general registers having addresses
R t + 1 and R2 + 1, respectively. Bit positions
register R2 + 1 contain the padding character. The
contents of bit positions
R t + 1 are ignored.
Graphically, the contents of the registers just de
scribed are as follows:
F irst-Operand Address
o 8 31
General Instructions 133