Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of L only)
Load Address
[RX]
41
o 8 12 16 20 31
The address specified by the X2, B2, and D2 fields is
inserted in bit positions 8-31 of the general register
specified by the R 1 field. Bits 0-7 of the register are
set to zeros. The address computation follows the
rules for address arithmetic.
No storage references for operands take place,
and the address is not inspected for access excep­
tions.
Condition Code:
The code remains unchanged.
Program Exceptions:
None.
Programming Note
The same general register may be specified by the
R 1, X2, and B2 instruction field, except that general
register 0 can be specified only by the Rl field. In
this manner it is possible to increment the low-order
24 bits of a general register, other than 0, by the
contents of the D2 field of the instruction. The regis­
ter to be incremented should be specified by Rl and
by either X2 (with B2 set to zero) or B2 (with X2 set
to zero).
Load and Test
LTR Rl,R2 [RR]
12
o 8 12 15
The second operand is placed unchanged in the first­
operand location, and the sign and magnitude of the
second operand determine the condition code.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
None.
Programming Note
When the Rl and R2 fields designate the same regis­
ter, the operation is equivalent to a test without data
movement.
Load Complement
LCR [RR]
o 8 12 15
The two's complement of the second operand is
placed in the first-operand location.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Program Exceptions:
Fixed-Point Overflow
Programming Note
Zero remains unchanged by complementation.
Load Hal/word
LH [RX]
48
o 8 12 16 20 31
The second operand is placed in the first-operand
location. The second operand is two bytes in length
and is considered to be a 16-bit signed integer.
The second operand is expanded to 32 bits by
propagating the sign-bit value through the 16 high­
order bit positions. Expansion occurs after the oper­
and is obtained from storage and before insertion in
the register.
General Instructions 131

Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Load lMultiple LM [R8]
The set of general registers starting with the register
specified by Rl and ending with the register speci­
fied by R3 is loaded from the locations designated by
the second-operand address.
The storage area from which the contents of the
general registers are obtained starts at the location
designated by the second-operand address and con­
tinues through as many locations as needed. The
general registers are loaded in the ascending order of
their addresses, starting with the register specified by
R 1 and (;ontinuing up to and including the register
specified by R3, with register 0 following register 15.
Conditi(Jln Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Programming Note
All combinations of register addresses specified by
R
1 and H .. 3 are valid. When the register addresses are
equal, only one word is transmitted. When the ad­
dress specified by R3 is less than the address speci­
fied by Rl, the register addresses wrap around from
15 to O. Load lVegative
LNR [RR]
The two's complement of the absolute value of the
second operand is placed in the first-operand loca­
tion.
The openition complements positive numbers;
negative numbers remain unchanged. The number
zero remains unchanged with positive sign.
132 System/370 Principles of Operation Resulting Condition Code: o Result is zero
1 Result is less than zero
2 -
3 -
Program Exceptions: None.
Load Positive
[RR] 10 o 8 12 15
The absolute value of the second operand is placed
in the first-operand location.
The operation includes complementation of nega­
tive numbers; positive numbers remain unchanged.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code: o Result is zero
1 -
2 Result is greater than zero
3 Overflow Program Exceptions:
Fixed-Point Overflow Monitor Call
[81]
AF 12 o 8 16
8, D, 20 A program interruption is caused if the appropriate
monitor-mask bit in control register 8 is one.
31
Bit positions 12-15 in the h field contain a binary
number specifying one of 16 monitoring classes.
When the monitor-mask bit corresponding to the
class specified by the h field is one, a program inter­
ruption for monitoring occurs. The contents of the h field are stored at location 149 of main storage, with
zeros stored at location 148. Bit 9 of the program
interruption code is set to one.
The address specified by the Bl and Dl fields
forms the monitor code, which is placed at locations