Shift Right Double SRDA The double-length integer part of the first operand is
shifted right the number of places specified by the
second-operand address. Bits 12-15 of the instruc­
tion are ignored.
The R 1 field of the instruction specifies an even­
odd pair of registers and must designate an even­ register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad­
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par­
ticipate in the shift in the same manner as the other
integer bits. The low-order bits are shifted out with­
out inspection and are lost. Bits equal to the sign are
supplied to the vacated positions of the registers. Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
Specification
Shift llight Double Logical SRDL Rl,D2(B2) [RS] The double-length first operand is shifted right the
number of bits specified by the second-operand ad­
dress. Bits 12-15 of the instruction are ignored.
The Rl field of the instruction specifies an even­
odd pair of registers and must designate an even­
numbered register. When Rl is odd, a specification
exception is recognized. 140 System/370 Principles of Operation The second-operand address is not used to ad­
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. Low-order bits are shifted out of the odd­
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Right Single
8A
o 8 12 16 20 31
The integer part of the first operand is shifted right
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to ad­
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
right shift. Bits equal to the sign are supplied to the
vacated high-order bit positions. Low-order bits are
shifted out without inspection and are lost.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: None
Programming Note
A right shift of one bit position is equivalent to divi­
sion by two with rounding downward. When an even
number is shifted right one position, the value of the
field is that obtained by dividing the value by 2.
When an odd number is shifted right one position,
the value of the field is that obtained by dividing the
next lower number by two. For example, +5 shifted
right by one bit position yields + 2, whereas -5 yields
-3.

Shift amounts from 31-63 cause the entire integer
to be spifted out of the register. When the entire
integer field of a positive number has been shifted­ out, the register contains a value of zero. For a nega­
tive number, the register contains a value of -1.
Shift Right Single Logical
SRL Rt,D2(B2) [RS]
88 R, 1883 B2 I o 8 12 16 20 The first operand is shifted right the number of bits
specified by the second-operand address. Bits 12-15
of the instruction are ignored.
The second-operand address is not used to ad-
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand participate in the
shift. Low-order bits are shifted out without inspec­
tion and are lost. Zeros are supplied to the vacated
high-order register positions.
Condition Code:
The code remains unchanged.
Program Exceptions:
None
Store
ST [RX] 50 o 8 12 16 20 The first operand is stored at the seGond-operand
location.
31
The 32 bits in the general register are placed un­
changed at the second-operand location.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Character
STC [RX]
42
o 8 12 16 20 31
The contents of bit positions 24-31 of the general
register designated by the Rt field are placed un­
changed at the second-operand location. The second
operand is one byte in length.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Characters Under Mask
BE R, I M3 I B2 D2
o 8 12 16 20 31
Bytes selected from the first operand under control
of a mask are placed in contiguous byte locations
beginning at the second-operand address.
The contents of the M3 field, bit positions 12-15,
are used as a mask. The four bits of the mask, left to
right, correspond one for one with the four bytes,
left to right, of the general register designated by the
R t field. The bytes corresponding to ones in the
mask are placed in the same order in successive and
contiguous storage locations beginning with the loca­
tion designated by the second-operand address. The
number of bytes stored is equal to the number of
ones in the mask. The contents of the general regis­
ter remain unchanged.
When the mask is not zero, exceptions associated
with storage-operand access are recognized only for
the number of bytes specified by the mask. When
the mask is zero, no access exceptions are recognized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Clock
STCK [S] 8205 o 16 20 31
The current value of the time-of-day clock is stored
at the eight-byte field designated by the second-
General Instructions 141